ATF-521P8-TR1 Avago Technologies US Inc., ATF-521P8-TR1 Datasheet - Page 14

• Manufacturer Part Number: ATF-521P8-TR1
• Description: IC PHEMT 2GHZ 4.5V 200MA 8-LPCC
• Manufacturer: Avago Technologies US Inc.

Specifications of ATF-521P8-TR1

• Gain: 17dB
• Transistor Type: pHEMT FET
• Frequency: 2GHz
• Voltage - Rated: 7V
• Current Rating: 500mA
• Noise Figure: 1.5dB
• Current - Test: 200mA
• Voltage - Test: 4.5V
• Power - Output: 26.5dBm
• Package / Case: 8-LPCC
• Power Dissipation Pd: 1.5W
• Rf Transistor Case: LPCC
• No. Of Pins: 8
• Frequency Max: 6GHz
• Noise Figure Typ: 1.5dB
• Frequency Min: 50MHz
• Continuous Drain Current Id: 14.8µA
• Configuration: Single Dual Source
• Drain-gate Voltage (max): -5 to 1V
• Operating Temperature (max): 150C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Drain Current Idss Max: 200mA
• Drain Source Voltage Vds: 4.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ATF-521P8 Applications Information
Description
Avago Technologies' ATF‑521P8 is an enhancement
mode PHEMT designed for high linearity and medium
power applications. With an OIP3 of 42 dBm and a 1dB
compression point of 26 dBm, ATF‑521P8 is well suited
as a base station transmit driver or a first or second
stage LNA in a receive chain. Whether the design is
for a W‑CDMA, CDMA, or GSM basestation, this device
delivers good linearity in the form of OIP3 or ACLR,
which is required for standards with high peak to
average ratios.
Application Guidelines
The ATF‑521P8 device operates as a normal FET
requiring input and output matching as well as DC
biasing. Unlike a depletion mode transistor, this en‑
hancement mode device only requires a single positive
power supply, which means a positive voltage is placed
on the drain and gate in order for the transistor to turn
on. This application note walks through the RF and DC
design employed in a single FET amplifier. Included in
this description is an active feedback scheme to accom‑
plish this DC biasing.
RF Input & Output Matching
In order to achieve maximum linearity, the appropri‑
ate input (Γ
presented to the device. Correctly matching from these
impedances to 50Ωs will result in maximum linearity.
Although ATF‑521P8 may be used in other impedance
systems, data collected for this data sheet is all refer‑
enced to a 50Ω system.
The input load pull parameter at 2 GHz is shown in
Figure 1 along with the optimum S11 conjugate match.
Figure 1. Input Match for ATF-521P 8
Figure 1. Input Match for ATF-521P8 at 2 GHz.
Thus, it should be obvious from the illustration above
that if this device is matched for maximum return
loss i.e. S11*, then OIP3 will be sacrificed. Conversely,
if ATF‑521P8 is matched for maximum linearity, then
14
S11
*
Γ
S
s
) and output (Γ
L
) impedances must be
GHz.
return loss will not be greater than 10 dB. For most ap‑
plications, a designer requires VSWR greater than 2:1,
hence limiting the input match close to S11*. Normally,
the input return loss of a single ended amplifier is not
critical as most basestation LNA and driver amplifiers
are in a balanced configuration with 90° (quadrature)
couplers.
Proceeding from the same premise, the output match
of this device becomes much simpler. As background
information, it is important to note that OIP3 is largely
dependant on the output match and that output return
loss is also required to be greater than 10 dB. So, Figure
2 shows how both good output return loss and good
linearity could be achieved simultaneously with the
same impedance point.
Of course, these points are valid only at 2 GHz, and
other frequencies will follow the same design rules but
will have different locations. Also, the location of these
points is largely due to the manufacturing process and
partly due to IC layout, but in either case beyond the
scope of this application note.
Figure 2. Output Match at 2 GHz.
Figure 2. Output Match
Once a designer has chosen the proper input and
output impedance points, the next step is to choose the
correct topology to accomplish this match. For example
to perform the above output impedance transformation
from 50Ω to the given load parameter of 0.53∠‑176°,
two possible solutions exist. The first potential match
is a high pass configuration accomplished by a shunt
inductor and a series capacitor shown in Figure 3 along
with its frequency response in Figure 4.
RF
Figure 3. High Pass Circuit Topology.
in
Γ
C1
S22*
L
L1
RF
ou t
at 2 GHz.