MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 706

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Electrical Characteristics
Figure 33-11
33.13.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)
The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. In addition,
the processor clock frequency must exceed twice the ETXCLK frequency.
Table 33-22
Figure 33-12
33-22
1
1
ETXCLK, ETXD0, and ETXEN have the same timing in 10 Mbit 7-wire interface mode.
Num
M5
M6
M7
M8
ERXDV, ERXCLK, and ERXD[0] have same timing in 10 Mbps 7-wire interface mode.
Num
M1
M2
M3
M4
lists MII transmit channel timings.
ETXCLK to ETXD[3:0], ETXEN, ETXER invalid
ETXCLK to ETXD[3:0], ETXEN, ETXER valid
ETXCLK pulse width high
ETXCLK pulse width low
shows MII receive signal timings listed in
ERXD[3:0] (inputs)
shows MII transmit signal timings listed in
ERXD[3:0], ERXDV, ERXER to ERXCLK setup
ERXCLK to ERXD[3:0], ERXDV, ERXER hold
ERXCLK pulse width high
ERXCLK pulse width low
ERXCLK (input)
ERXDV
ERXER
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 33-11. MII Receive Signal Timing Diagram
Characteristic
Characteristic
Table 33-22. MII Transmit Signal Timing
Table 33-21. MII Receive Signal Timing
M1
1
1
M2
M3
Table
Table
33-21.
33-22.
35%
35%
Min
—
35%
35%
M4
5
Min
5
5
Max
65%
65%
25
—
65%
65%
Max
—
—
Freescale Semiconductor
ERXCLK period
ERXCLK period
ETXCLK period
ETXCLK period
Unit
Unit
ns
ns
ns
ns