MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 180

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Clock Module
9.7
This subsection provides a functional description of the clock module.
9.7.1
The system clock source is determined during reset (see
latched during reset and are of no importance after reset is negated. If CLKMOD1 or CLKMOD0 is
changed during a reset other than power-on reset, the internal clocks may glitch as the system clock source
is changed between external clock mode and PLL clock mode. Whenever CLKMOD1 or CLKMOD0 is
changed in reset, an immediate loss-of-lock condition occurs.
Table 9-7
modes.
9-10
Bit(s)
1–0
2
Functional Description
shows the clockout frequency to clockin frequency relationships for the possible system clock
System Clock Modes
Normal PLL clock mode
1:1 PLL clock mode
External clock mode
PLLMODE:PLLSEL:PLLREF
Name
LOCS
—
System Clock Mode
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
000
100
110
111
Table 9-5. SYNSR Field Descriptions (continued)
Table 9-7. Clock Out and Clock In Relationships
Sticky indication of whether a loss-of-clock condition has occurred at any time since
exiting reset in normal PLL and 1:1 PLL modes. LOCS = 0 when the system clocks
are operating normally. LOCS = 1 when system clocks have failed due to a reference
failure or PLL failure.
After entering stop mode with FWKUP set and the PLL and oscillator intentionally
disabled (STPMD[1:0] = 11), the PLL exits stop mode in the SCM while the oscillator
starts up. During this time, LOCS is temporarily set regardless of LOCEN. It is cleared
once the oscillator comes up and the PLL is attempting to lock.
If a read of the LOCS flag and a loss-of-clock condition occur simultaneously, the flag
does not reflect the current loss-of-clock condition.
A loss-of-clock condition can be detected only if LOCEN = 1 or the oscillator has not
yet returned from exit from stop mode with FWKUP = 1.
1 Loss-of-clock detected since exiting reset or oscillator not yet recovered from exit
0 Loss-of-clock not detected since exiting reset
Note: The LOCS flag is always 0 in external clock mode.
Reserved, should be cleared.
from stop mode with FWKUP = 1
Table 9-6. System Clock Modes
External clock mode
1:1 PLL mode
Normal PLL mode with external clock reference
Normal PLL mode with crystal reference
f
f
f
sys
sys
sys
= f
= f
= f
ref
ref
ref
Table
× 2(MFD + 2)/2
Description
Clock Mode
27-8). The values of CLKMOD[1:0] are
PLL Options
RFD
1
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