MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 589

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Queued Analog-to-Digital Converter (QADC)
polarity of the external trigger signal is programmable, so that a mode which begins queue execution on
the rising or falling edge can be selected. Each CCW is read and the indicated conversions are performed
until an end-of-queue condition is encountered. When the next external trigger edge is detected, queue
execution begins again automatically. Software involvement is not needed between trigger events.
When a pause bit is encountered in externally triggered continuous-scan mode, another trigger event is
required for queue execution to continue. Software involvement is not needed for queue execution to
continue from the paused state.
Some applications need to synchronize the sampling of analog channels to external events. There are cases
when it is not possible to use software initiation of the queue scan sequence, because interrupt response
times vary. Externally triggered continuous-scan mode is useful in these cases.
28.8.7.3 Externally Gated Continuous-Scan Mode
The QADC provides external gating for queue 1 only. When externally gated continuous-scan mode is
selected, the input level on the associated external trigger signal enables and disables queue execution. The
polarity of the external gate signal is fixed so that a high level opens the gate and a low level closes the
gate. Once the gate is open, each CCW is read and the indicated conversions are performed until the gate
is closed. When the gate opens again, queue execution automatically restarts at the beginning of the queue.
Software involvement is not needed between trigger events. If a pause in a CCW is encountered, the pause
flag does not set, and execution continues without pausing.
The purpose of externally gated continuous-scan mode is to continuously collect digitized samples while
the gate is open and to have the most recent samples available. It is up to the programmer to ensure that
the gate is not opened so long that an end-of-queue is reached.
In the event that the queue completes before the gate closes, the CF1 flag will set, and the queue will roll
over to the beginning and continue conversions until the gate closes. If the gate remains open and the CF1
flag is not cleared, when the queue completes a second time the TOR1 flag will set and the queue will
roll-over again. The queue will continue to execute until the gate closes or the mode is disabled.
If the gate closes before queue 1 completes execution, the QADC stops and sets the PF1 bit to indicate an
incomplete queue. The CWPQ1 field can be read to determine the last valid conversion in the queue. If the
gate opens again, execution of queue 1 restarts. The start of queue 1 is always the first CCW in the CCW
table. The condition of the gate is only sampled after each conversion during queue execution, so closing
the gate for a period less than a conversion time interval does not guarantee the closure will be captured.
28.8.7.4 Periodic Timer Continuous-Scan Mode
The QADC includes a dedicated periodic timer for initiating a scan sequence on queue 1 and/or queue 2.
7
17
A programmable timer interval ranging from 2
to 2
times the QCLK period in binary multiples can be
selected. The QCLK period is prescaled down from the MCU clock.
When a periodic timer continuous-scan mode is selected, the timer begins counting. After the programmed
interval elapses, the timer generated trigger event starts the appropriate queue. The QADC automatically
performs the conversions in the queue until an end-of-queue condition or a pause is encountered. When a
pause occurs, the QADC waits for the periodic interval to expire again, then continues with the queue.
Once EOQ has been detected, the next trigger event causes queue execution to restart with the first CCW
in the queue.
The periodic timer generates a trigger event whenever the time interval elapses. The trigger event may
cause queue execution to continue following a pause or queue completion or may be considered a trigger
overrun. As with all continuous-scan queue operating modes, software action is not needed between
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor
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