MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 308

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

DMA Controller Module
16.5.2
Each channel supports dual-address transfers, described in the next section.
16.5.2.1 Dual-Address Transfers
Dual-address transfers consist of a source data read and a destination data write. The DMA controller
module begins a dual-address transfer sequence during a DMA request. If no error condition exists,
DSRn[REQ] is set.
16.5.3
Before a block transfer starts, channel registers must be initialized with information describing
configuration, request-generation method, and the data block.
16.5.3.1 Channel Prioritization
The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel
3 having the lowest) or in an order determined by DCRn[BWC]. If the BWC encoding for a DMA channel
is 000, that channel has priority only over the channel immediately preceding it. For example, if
DCR3[BWC] = 000, DMA channel 3 has priority over DMA channel 2 (assuming DCR2[BWC] ≠ 000)
but not over DMA channel 1.
If DCR0[BWC] = DCR1[BWC] = 000, DMA0 still has priority over DMA1. In this case, DCR1[BWC] =
000 does not affect prioritization.
Simultaneous external requests are prioritized either in ascending order or in an order determined by each
channel’s DCRn[BWC] bits.
16.5.3.2 Programming the DMA Controller Module
Note the following general guidelines for programming the DMA:
The SARn is loaded with the source (read) address. If the transfer is from a peripheral device to memory,
the source address is the location of the peripheral data register. If the transfer is from memory to either a
16-12
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Dual-address read—The DMA controller drives the SARn value onto the internal address bus. If
DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon a successful
read cycle. When the appropriate number of read cycles complete (multiple reads if the destination
size is larger than the source), the DMA initiates the write portion of the transfer.
If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop.
Dual-address write—The DMA controller drives the DARn value onto the address bus. If
DCRn[DINC] is set, DARn increments by the appropriate number of bytes at the completion of a
successful write cycle. BCRn decrements by the appropriate number of bytes. DSRn[DONE] is set
when BCRn reaches zero. If the BCRn is greater than zero, another read/write transfer is initiated.
If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of
the bus cycle to allow the internal arbiter to switch masters.
If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop.
No mechanism exists within the DMA module itself to prevent writes to control registers during
DMA accesses.
If the DCRn[BWC] value of sequential channels are equal, the channels are prioritized in
ascending order.
Data Transfer Modes
Channel Initialization and Startup
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor