TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 693

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

(4)
(5)
cepted while it is in an automatic block erase operation. If it is desired to stop operation, use the hard-
ware reset function. In this case, it is necessary to perform the automatic block erase operation
again because the data erasing operation has not been normally terminated.
flash memory is locked in the mode and will not return to the read mode. In this case, execute hard-
ware reset to reset the device.
ble 22-18 for table of protection bit addresses. This device assigns 1 bit to 1 block as a protection
bit. The applicable protection bit is specified by PBA in the seventh bus write cycle. By automatical-
ly programming the protection bits, write and/or erase functions can be inhibited (for protection) indi-
vidually for each block. The protection status of each block can be checked by FCFLCS <BLPRO>
to be described later. This status of the automatic programming operation to set protection bits can
be checked by monitoring FCFLCS <RDY/BSY>. Any new command sequence is not accepted
while automatic programming is in progress to program the protection bits. If it is desired to stop
the programming operation, use the hardware reset function. In this case, it is necessary to perform
the programming operation again because the protection bits may not have been correctly program-
med. If all the protection bits have been programmed, all FCFLCS <BLPRO> are set to "1" indicat-
ing that it is in the protected state. This disables subsequent writing and erasing of all blocks.
pending on the status of the protection bits and the security bits. It depends on whether all
<BLPRO> in the FCFLCS register are set to "1" or not, when FCSECBIT<FCSECBIT> is set to
"1". Be sure to check the value of FCFLCS <BLPRO> before executing the automatic protection
bit erase command. See Chapter "Protect/security function" for details.
Also, any protected block cannot be erased. If an automatic block erase operation has failed, the
This device is implemented with protection bits. This protection can be set for each block. See Ta-
Different results will be obtained when the automatic protection bit erase command is executed de-
Note:Software reset is ineffective in the seventh bus write cycle of the automatic protection
Automatic programming of protection bits (for each block)
Automatic erasing of protection bits
・ When all the FCFLCS <BLPRO> are set to "1" (all the protection bits are programmed):
・ When FCFLCS <BLPRO> include "0" (not all the protection bits are programmed):
bit programming command. FCFLCS <RDY/BSY> turns to "0" after entering the sev-
enth bus write cycle.
ry is automatically initialized within the device. When the seventh bus write cycle is comple-
ted, the entire area of the flash memory data cells is erased and then the protection bits are
erased. This operation can be checked by monitoring FCFLCS <RDY/BSY>. If the automat-
ic operation to erase protection bits is normally terminated, FCFLCS will be set to
"0x00000001". Since no automatic verify operation is performed internally to the device,
be sure to read the data to confirm that it has been correctly erased. For returning to the
read mode while the automatic operation after the seventh bus cycle is in progress, it is nec-
essary to use the hardware reset to reset the device. If this is done, it is necessary to check
the status of protection bits by FCFLCS <BLPRO> after retuning to the read mode and per-
form either the automatic protection bit erase, automatic chip erase, or automatic block
erase operation, as required.
With this device, protection bits can be programmed to an individual block and performed
bit-erase operation in the four bits unit as shown in Table 22-18. The target bits are speci-
fied in the seventh bus write cycle.The protection status of each block can be checked by
FCFLCS <BLPRO> to be described later. This status of the programming operation for au-
tomatic protection bits can be checked by monitoring FCFLCS <RDY/BSY>. When the au-
tomatic operation to erase protection bits is normally terminated, the protection bits of
FCFLCS <BLPRO> selected for erasure are set to "0".
When the automatic protection bit erase command is command written, the flash memo-
If the automatic protection bit is cleared to "0", the protection condition is canceled.
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TMPM362F10FG