TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 692

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

22.3
On-board Programming of Flash Memory (Rewrite/Erase)
(2)
(3)
the 32-bit data transfer command in writing commands after the fourth bus cycle. At this time, any
32-bit data transfer commands shall not be placed across word boundary. After the fifth bus write cy-
cle, data is command written to the same page area. Even if it is desired to write the page only parti-
ally, it is required to perform the automatic page programming for the entire page. In this case, the ad-
dress input for the fourth bus write cycle shall be set to the top address of the page. Be sure to per-
form command write operation with the input data set to "1" for the data cells not to be set to "0".
For example, if the top address of a page is not to be written, set the input data in the fourth bus
write cycle to 0xFFFFFFFF as a command write.
tion can be checked by monitoring FCFLCS<RDY / BSY>. Any new command sequence is not accep-
ted while it is in automatic page programming mode. If it is desired to stop operation, use the hard-
ware reset function. Be careful in doing so because data cannot be written normally if the operation
is interrupted. When a single page has been command written with normally terminating the automat-
ic page writing process, FCFLCS<RDY / BSY> is set to "1" then it returns to the read mode.
mand for each page because the number of pages to be written by a single execution of the automat-
ic page program command is limited to only one page. It is not allowed for automatic page program-
ming to process input data across pages.
ically returns to the read mode. This condition can be checked by monitoring FCFLCS<RDY/
BSY>. If automatic programming has failed, the flash memory is locked in the current mode and
will not return to the read mode. For returning to the read mode, it is necessary to execute hardware
reset to reset the flash memory or the device. In this case, while writing to the address has failed, it
is recommended not to use the device or not to use the block that includes the failed address.
completed.
operation is performed internally to the device, be sure to read the data to confirm that data has
been correctly erased. Any new command sequence is not accepted while it is in an automatic chip
erase operation. If it is desired to stop operation, use the hardware reset function. If the operation is
forced to stop, it is necessary to perform the automatic chip erase operation again because the data eras-
ing operation has not been normally terminated.
erase operation will not be performed and it returns to the read mode after completing the sixth bus
read cycle of the command sequence. When an automatic chip erase operation is normally termina-
ted, it automatically returns to the read mode. If an automatic chip erase operation has failed, the
flash memory is locked in the current mode and will not return to the read mode.
this case, the failed block cannot be detected. It is recommended not to use the device anymore or
to identify the failed block by using the block erase function for not to use the identified block anymore.
is completed.
<RDY / BSY>. While no automatic verify operation is performed internally to the device, be sure
to read the data to confirm that data has been correctly erased. Any new command sequence is not ac-
Once the third bus cycle is executed, the automatic page programming is in operation. This condi-
When multiple pages are to be written, it is necessary to execute the page programming com-
Data cannot be written to a protected block. When automatic programming is finished, it automat-
The automatic chip erase operation starts when the sixth bus write cycle of the command cycle is
This condition can be checked by monitoring FCFLCS<RDY / BSY>. While no automatic verify
Also, any protected block cannot be erased. If all the blocks are protected, the automatic chip
For returning to the read mode, it is necessary to execute hardware reset to reset the device. In
The automatic block erase operation starts when the sixth bus write cycle of the command cycle
This status of the automatic block erase operation can be checked by monitoring FCFLCS
Note:Software reset becomes ineffective after the fourth bus write cycle of the automatic
Automatic chip erase
Automatic block erase (for each block)
page programming command.
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TMPM362F10FG