TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 300

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

9.2
DMA transfer type
9.2
Table 9-2 DMA transfer type
1
2
3
Memory → peripher-
Peripheral circuit →
Memory → memory
Note 1: SSP: Peripheral circuit corresponding to the single request
Note 2: For supported DMA requests, refer to later pages.
DMA transfer type
DMA direction
al circuit
memory
peripheral circuit
peripheral circuit
DMA request
(Destination)
(Source)
DMAC
circuit
Burst request /
single request
DMA request
Burst request
Support
(Note2)
(Note1)
−
Page 276
In case of 1word transmission, set to the "1" for burst size of DMA controller.
If the amount of data transfer is not an integer multiples of the burst size,
both burst and single transfers can be used.
If the amount of data transfer defined with DMA controller is the same size of
the burst size or more, the single request is ignored and the burst transfer is tak-
en place.
If the amount of data transfer defined with DMA controller is less than the
burst size, the single burst transfer is taken place.
No DMA request occurs.
When DMA circuit is enabled, data transfer starts.
(Memory to memory transfer is selected and DMACCxConfiguration<E> = 1
is set.)
When all data transfer is comple or DMA channel is disabled, data transfer
stops.
Other condtion
TMPM362F10FG