TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 463

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

13.5
13.5.1
13.5.2
13.5.3
SSP operation
one of the following protocols. In addition, make the settings related to the communication speed in the
clock prescale registers SSPCPSR and SSPCR0 <SCR>.
mit FIFO, or when transmitted data is written in the transmit FIFO with the operation enabled.
mit interrupt will be generated. This interrupt can be used to write the initial data.
Settings for the SSP communication protocol must be made with the SSP disabled.
Control registers SSPCR0 and SSPCR1 need to configure this SSP as a master or slave operating under
This SSP supports the following protocols:
The transfer operation starts when the operation is enabled with the transmitted data written in the trans-
However, if the transmit FIFO contains only four or fewer entries when the operation is enabled, a trans-
When setting a frequency for fsys , the following conditions must be met.
Initial setting for SSP
Enabling SSP
Clock ratios
Note:When the SSP is in the SPI slave mode and the SPFSS pin is not used, be sure to transmit data of
Note:The maximum baud-rate in the master mode is equal or less than 10Mbps.
・ SPI
・ SSI
・ Microwire
・ In master mode
・ In slave mode
one byte or more in the FIFO before enabling the operation. If the operation is enabled with the trans-
mit FIFO empty, the transfer data will not be output correctly.
f
f
f
f
SPCLK
SPCLK
SPCLK
SPCLK
(minimum) → f
(maximum) → f
(minimum) → f
(maximum) → f
sys
sys
sys
sys
/(254×256)
/(254×256)
/4
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TMPM362F10FG