TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 378

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

11.6
Description of Operations for Each Mode
11.6.4
TBxEN
TBxRUN
TBxCR
TBxRG0
TBxRG1
TBxCR
TBxFFCR
TBxMOD
Set PORT registers.
TBxRUN
Note 1: m ; corresponding bit of port
Note 2: X; Don’t care
The block diagram of this mode is shown below.
Each register in the 16-bit PPG output mode must be programmed as listed below.
This mode enables the timers to start synchronously.
Timer synchronous mode
TBxRG0
TBxIN0
Write
−; No change
φT16
←
←
←
←
←
←
←
←
←
←
←
TBxCR<TBWBF>
φT1
φT4
7
1
X
0
*
*
*
*
1
X
X
*
Selector
Figure 11-5 Block Diagram of 16-bit PPG Mode
Selector
6
X
X
0
*
*
*
*
0
X
0
*
5
X
X
−
*
*
*
*
−
0
1
*
16-bit comparetor
Register buffer0
4
X
X
X
*
*
*
*
X
0
0
*
TBxRG0
3
X
X
−
*
*
*
*
−
1
0
*
(** = 01, 10, 11)
2
X
0
X
*
*
*
*
X
1
1
1
16-bit up-counter
Internal data bus
1
X
X
0
*
*
*
*
0
1
*
X
Match
TBxRG1
UC
Write
0
X
0
0
*
*
*
*
0
0
*
1
Page 354
TBxCR<TBWBF>
Selector
Enables TMRBx operation.
Stops count operation.
Disable double buffering.
Specifies a duty. (16 bits))
Specifies a cycle. (16 bits)
Enables the TBxRG0 double buffering.
(Changes the duty / cycle when the INTTBx interrupt is gener-
ated)
Specifies to trigger TBxFF0 to reverse when a match with
TBxRG0 or TBxRG1 is detected, and sets the initial value of
TBxFF0 to "0".
Designates the prescaler output clock as the input clock, and
disables the capture function.
Allocates corresponding port to TBxOUT.
Starts TMRBx.
TBxRUN<TBRUN>
16-bit comparetor
Register buffer1
Clear
TBxRG1
TBxOUT (PPG
(TBxFF0)
F/F
TMPM362F10FG
)