SAF-C515C-8EM CA Infineon Technologies, SAF-C515C-8EM CA Datasheet - Page 64

• Manufacturer Part Number: SAF-C515C-8EM CA
• Description: IC MCU 8BIT OTP MQFP-80-1
• Manufacturer: Infineon Technologies
• Series: C5xx/C8xxr

Specifications of SAF-C515C-8EM CA

• Core Processor: C500
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: OTP
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 4.25 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-SQFP
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: USART, SSC
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-80
• Max Clock Frequency: 10.0 MHz
• Sram (incl. Cache): 2.25 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 64.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: F515C8EMCANP; F515C8EMCAXT; SAF-C515C-8EMCA; SAF-C515C-8EMCA; SAF-C515C-8EMCAIN; SAFC515C8EMCAX; SP000068749; SP000106399

The following
are required for OTP memory programming.
Table 12
Symbol
RESET
PMSEL0
PMSEL1
PSEL
PRD
PALE
XTAL2
XTAL1
Data Sheet
Pin Number I/O
1
15
16
17
18
19
36
37
Table 12
Pin Definitions and Functions in Programming Mode
contains the functional description of all C515C-8E pins which
I
I
I
I
I
I
I
O
1)
PMSEL1
0
0
1
1
Function
Reset
This input must be at static “0” (active) level during the
whole programming mode.
Programming mode selection pins
These pins are used to select the different access
modes in programming mode. PMSEL1,0 must satisfy
a setup time to the rising edge of PALE. When the logic
level of PMSEL1,0 is changed, PALE must be at low
level.
Basic programming mode select
This input is used for the basic programming mode
selection and must be switched according
Programming mode read strobe
This input is used for read access control for OTP
memory read, version byte read, and lock bit read
operations.
Programming address latch enable
PALE is used to latch the high address lines. The high
address lines must satisfy a setup and hold time to/from
the falling edge of PALE. PALE must be at low level
whenever the logic level of PMSEL1,0 is changed.
XTAL2
Input to the oscillator amplifier.
XTAL1
Output of the inverting oscillator amplifier.
60
PMSEL0 Access Mode
0
1
0
1
Reserved
Read version bytes
Program/read lock bits
Program/read OTP memory
byte
Figure
C515C
2003-02
27.