SAF-C515C-8EM CA Infineon Technologies, SAF-C515C-8EM CA Datasheet - Page 57

• Manufacturer Part Number: SAF-C515C-8EM CA
• Description: IC MCU 8BIT OTP MQFP-80-1
• Manufacturer: Infineon Technologies
• Series: C5xx/C8xxr

Specifications of SAF-C515C-8EM CA

• Core Processor: C500
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: OTP
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 4.25 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-SQFP
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: USART, SSC
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-80
• Max Clock Frequency: 10.0 MHz
• Sram (incl. Cache): 2.25 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 64.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: F515C8EMCANP; F515C8EMCAXT; SAF-C515C-8EMCA; SAF-C515C-8EMCA; SAF-C515C-8EMCAIN; SAFC515C8EMCAX; SP000068749; SP000106399

Fail Save Mechanisms
The C515C offers two on-chip peripherals which monitor the program flow and ensure
an automatic “fail-safe” reaction for cases where the controller’s hardware fails or the
software hangs up:
• A programmable watchdog timer (WDT) with variable time-out period from
• An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
Programmable Watchdog Timer
The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate
of
upper 7 bit of the watchdog timer can be written.
the watchdog timer unit.
Figure 23
The watchdog timer can be started by software (bit SWDT) or by hardware through pin
PE/SWD, but it cannot be stopped during active mode of the C515C. If the software fails
to refresh the running watchdog timer an internal reset will be initiated on watchdog timer
overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is
transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of
Data Sheet
512 microseconds up to approx. 1.1 seconds at 6 MHz.
microcontroller into reset state in case the on-chip oscillator fails; it also provides the
clock for a fast internal reset after power-on.
f
OSC
/12 up to
f
WDT Reset Request
External HW Reset
External HW Power-Down
PE/SWD
OSC
-
-
-
/6
WDTS
SWDT
WDT
Block Diagram of the Programmable Watchdog Timer
f
OSC
-
-
-
÷2
/192. For programming of the watchdog timer overflow rate, the
Control Logic
-
-
-
-
-
-
-
-
-
÷16
-
-
-
IP0 (A9 ) H
53
-
-
-
IEN0 (A8 )
IEN1 (B8 )
Figure 23
WDTPSEL
H
H
0
7 6
shows the block diagram of
14
WDTREL (86 )
WDTL
WDTH
MCB02755
H
7
8
0
C515C
2003-02