UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 486

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(2) Error of baud rate
(3) Example of setting baud rate
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
115200
153600
312500
625000
19200
24000
31250
38400
48000
76800
Baud
1200
2400
4800
9600
Rate
[bps]
300
600
Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (f
The baud rate error can be calculated by the following expression.
• Error (%) =
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the
Example: Frequency of base clock = 10 MHz = 10,000,000 Hz
TPS63-
TPS60
8H
7H
6H
5H
4H
3H
2H
1H
1H
1H
0H
0H
0H
−
−
−
k:
f
ERR:
PRS
2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible
f
PRS
Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)
Target baud rate = 153600 bps
Baud rate = 10 M / (2 × 33)
Error = (151515/153600 − 1) × 100
13
13
13
13
13
13
13
21
16
13
21
13
k
9
−
−
−
:
= 2.0 MHz
reception destination.
baud rate range during reception.
Actual baud rate (baud rate with error)
Calculated
Desired baud rate (correct baud rate)
111111 −3.55
19231
23810
38462
47619
76923
= −1.357 [%]
31250
Value
1202
2404
4808
9615
301
601
−
−
−
= 10000000 / (2 × 33) = 151,515 [bps]
−0.79
−0.79
ERR
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
[%]
0
−
−
−
Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k
= 4, 5, 6, ..., 255)
Peripheral hardware clock frequency
Baud rate error
TPS63-
TPS60
Table 15-5. Set Data of Baud Rate Generator
7H
6H
5H
4H
3H
2H
1H
3H
0H
2H
0H
1H
1H
0H
0H
4H
f
PRS
65
65
65
65
65
65
65
13
65
13
33
11
k
5
8
8
4
= 5.0 MHz
Calculated
113636 −1.36
156250
312500
625000
19231
24038
31250
38462
48077
75758
Value
1202
2404
4808
9615
301
601
−1.36
ERR
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
1.73
[%]
− 1 × 100 [%]
0
0
0
TPS63-
TPS60
8H
7H
6H
5H
4H
3H
2H
4H
5H
1H
3H
0H
0H
0H
1H
1H
f
CHAPTER 15 SERIAL INTERFACE UART6
PRS
65
65
65
65
65
65
65
13
65
13
65
43
33
k
5
8
4
= 10.0 MHz
Calculated
116279
151515 −1.36
312500
625000
19231
24038
31250
38462
48077
76923
Value
1202
2404
4808
9615
301
601
ERR
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.94
[%]
0
0
0
TPS63-
TPS60
7H
6H
5H
4H
3H
9H
8H
5H
6H
2H
4H
1H
0H
1H
2H
2H
f
PRS
65
65
65
65
65
65
65
13
65
13
65
87
33
k
5
8
4
= 20.0 MHz
Calculated
114943 −0.22
151515 −1.36
312500
625000
19231
24038
31250
38462
48077
76923
Value
XCLK6
1202
2404
4808
9615
301
601
))
ERR
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
[%]
0
0
0
486