UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 455

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
The length of the sync field transmitted from the LIN master can be measured using the external event capture operation
of 16-bit timer/event counter 00, and the baud rate error can be calculated.
counter 00 by port input switch control (ISC0/ISC1), without connecting R
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Reception interrupt
Reception processing is as follows.
Figure 15-3 shows the port configuration for LIN reception operation.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0).
The input source of the reception port input (R
<1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode.
<2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has
<3> If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter 00
<4> Calculate the baud rate error from the bit interval of the sync field, disable UART6 after SF reception, and then
<5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after
Edge detection
Capture timer
been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output.
If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error
has occurred. The interrupt signal is not output and the SBF reception mode is restored.
by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field (see
7.4.8 Pulse width measurement operation). Detection of errors OVE6, PE6, and FE6 is suppressed, and
error detection processing of UART communication and data transfer of the shift register and RXB6 is not
performed. The shift register holds the reset value FFH.
re-set baud rate generator control register 6 (BRGC6).
reception of the checksum field and to set the SBF reception mode again.
(INTSR6)
LIN Bus
(INTP0)
(input)
R
X
D6
Disable
signal frame
<1>
Wakeup
Enable
Figure 15-2. LIN Reception Operation
Disable
SBF reception
break field
X
13-bit
Sync
<2>
D6) can be input to the external interrupt (INTP0) and 16-bit timer/event
<3>
Sync field
reception
SF
Enable
<4>
CHAPTER 15 SERIAL INTERFACE UART6
X
D6 and INTP0/TI000 externally.
reception
Identifier
field
ID
Data field
reception
Data
Data field Checksum
reception
Data
reception
field
Data
<5>
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