UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 252

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clock
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal
<1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register)
<2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM register)
Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal
high-speed oscillation clock or high-speed system clock as peripheral hardware clock
<1> • Restarting oscillation of the internal high-speed oscillation clock
<2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register)
<3> Selecting the CPU clock division ratio (PCC register)
When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating.
Wait until RSTS is set to 1
• Oscillating the high-speed system clock
Set the main system clock and peripheral hardware clock using XSEL and MCM0.
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division
ratio, use PCC0, PCC1, and PCC2.
2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral
(See 6.6.2 (1) Example of setting procedure when restarting oscillation of the internal high-speed
oscillation clock).
(This setting is required when using the high-speed system clock as the peripheral hardware clock. See
6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting
procedure when using the external main system clock.)
Note The setting of <1> is not necessary when the internal high-speed oscillation clock or high-speed
XSEL
CSS
high-speed oscillation clock is selected as the CPU clock.
hardware clock.
0
0
1
0
system clock is already operating.
MCM0
PCC2
0
1
0
0
0
0
0
1
Other than above
Internal high-speed oscillation clock
(f
Selection of Main System Clock and Clock Supplied to Peripheral Hardware
RH
Note 2
PCC1
)
0
0
1
1
0
.
Main System Clock (f
PCC0
0
1
0
1
0
Note
f
f
f
f
f
Setting prohibited
XP
XP
XP
XP
XP
XP
)
/2 (default)
/2
/2
/2
2
3
4
CPU Clock (f
Internal high-speed oscillation clock
(f
High-speed system clock (f
RH
Peripheral Hardware Clock (f
)
Note
CHAPTER 6 CLOCK GENERATOR
CPU
) Selection
XH
)
PRS
)
Note 1
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