UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 447

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
R
X
(e) Reception error
(f) Noise filter of receive data
D0/SI10/P11
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of
asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a
reception error interrupt (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception
error interrupt (INTSR0) servicing (see Figure 14-3).
The contents of ASIS0 are cleared to 0 when ASIS0 is read.
The R
If two sampled values are the same, the output of the match detector changes, and the data is sampled as input
data.
Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation is
delayed by two clocks from the external signal status.
Parity error
Framing error
Overrun error
Base clock
X
D0 signal is sampled using the base clock output by the prescaler block.
Reception Error
The parity specified for transmission does not match the parity of the receive data.
Stop bit is not detected.
Reception of the next data is completed before data is read from receive buffer
register 0 (RXB0).
In
Table 14-3. Cause of Reception Error
Figure 14-10. Noise Filter Circuit
Q
Internal signal A
Match detector
CHAPTER 14 SERIAL INTERFACE UART0
Cause
In
LD_EN
Q
Internal signal B
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