UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 356

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
8.4.2 Operation as external event counter
5n (TM5n).
rising or falling edge can be selected.
interrupt request signal (INTTM5n) is generated.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter
TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the
When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an
Whenever the TM5n value matches the value of CR5n, INTTM5n is generated.
<1> Set each register.
<2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted.
<3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match.
Note 8-bit timer/event counter 50: PM17
Remark For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Setting
TM5n count value
• Set the port mode register (PM17 or PM33)
• TCL5n: Select TI5n pin input edge.
• CR5n:
• TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and
Remark N = 00H to FFH
8-bit timer/event counter 51: PM33
INTTM5n
Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified)
CR5n
TI5n
n = 0, 1
TI5n pin falling edge → TCL5n = 00H
TI5n pin rising edge → TCL5n = 01H
Compare value
CR5n, disable the timer F/F inversion operation, disable timer output.
(TMC5n = 00000000B)
Count start
00H
01H
02H
03H
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
04H
Note
to 1.
05H
N
1
N
N
00H
01H
02H
03H
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