UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 268

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
6.6.9 Conditions before clock oscillation is stopped
conditions before the clock oscillation is stopped.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
Note The 78K0/KB2 is not provided with a subsystem clock.
Internal high-speed
oscillation clock
X1 clock
External main system clock
Internal high-speed
oscillation clock
X1 clock
External main system clock
XT1 clock
External subsystem clock
Table 6-11. Conditions Before the Clock Oscillation Is Stopped and Flag Settings (78K0/KB2)
Clock
Clock
Note
Table 6-12. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
MCS = 1
(The CPU is operating on the high-speed system clock)
MCS = 0
(The CPU is operating on the internal high-speed oscillation clock)
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock)
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
CLS = 0
(The CPU is operating on a clock other than the subsystem clock)
(78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Conditions Before Clock Oscillation Is Stopped
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
(External Clock Input Disabled)
CHAPTER 6 CLOCK GENERATOR
RSTOP = 1
MSTOP = 1
RSTOP = 1
MSTOP = 1
OSCSELS = 0
Flag Settings of SFR
Flag Settings of SFR
Register
Register
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