MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 67

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

4.5 Memory Organization
M68HC16 Z SERIES
USER’S MANUAL
Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit.
Bits [34:31] are sign extension bits. There is an implied radix point between bits 31 and
30. There are 31 bits of magnitude, but use of the extension bits allows representation
of numbers in the range –16 ($800000000) to 15.999969482 ($7FFFFFFFF).
Both program and data memory are divided into sixteen 64-Kbyte banks. Addressing
is linear. A 20-bit extended address can access any byte location in the appropriate
address space.
A word is composed of two consecutive bytes. A word address is normally an even
byte address. Byte 0 of a word has a lower 16-bit address than byte 1. Long words and
32-bit signed fractions consist of two consecutive words, and are normally accessed
at the address of byte 0 in word 0.
Instruction fetches always access word addresses. Word operands are normally ac-
cessed at even byte addresses, but can be accessed at odd byte addresses, with a
substantial performance penalty.
To permit compatibility with the M68HC11, misaligned word transfers and misaligned
stack accesses are allowed. Transferring a misaligned word requires two successive
byte transfer operations.
Figure 4-3
even addresses show size and alignment.
shows how each CPU16 data type is organized in memory. Consecutive
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