MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 147

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.6.4.1 Breakpoint Acknowledge Cycle
M68HC16 Z SERIES
USER’S MANUAL
Breakpoints stop program execution at a predefined point during system development.
In M68HC16 Z-series MCUs, breakpoints are treated as a type of exception process-
ing. Breakpoints can be used alone or in conjunction with background debug mode.
M68HC16 Z series MCUs have only one source and type of breakpoint. This is a hard-
ware breakpoint initiated by assertion of the BKPT input. Other modular microcontrol-
lers may have more than one source or type. The breakpoint acknowledge cycle
discussed here is the bus cycle that occurs as a part of breakpoint exception process-
ing when a breakpoint is initiated while background debug mode is not enabled.
BKPT is sampled on the same clock phase as data. BKPT is valid, the data is tagged
as it enters the CPU16 pipeline. When BKPT is asserted while data is valid during an
instruction prefetch, the acknowledge cycle occurs immediately after that instruction
has executed. When BKPT is asserted while data is valid during an operand fetch, the
acknowledge cycle occurs immediately after execution of the instruction during which
it is latched. If BKPT is asserted for only one bus cycle and a pipe flush occurs before
BKPT is detected by the CPU16, no acknowledge cycle occurs. To ensure detection,
BKPT should be asserted until a breakpoint acknowledge cycle is recognized.
When BKPT assertion is acknowledged by the CPU16, the MCU performs a word read
from CPU space address $00001E. This corresponds to the breakpoint number field
(ADDR[4:2]) and the type bit (T) being set to all ones (source 7, type 1). If this bus cycle
is terminated by BERR or by DSACK, the MCU performs breakpoint exception pro-
cessing. Refer to
SIM Reference Manual (SIMRM/AD) for further information.
STOP BROADCAST
ACKNOWLEDGE
ACKNOWLEDGE
BREAKPOINT
LOW POWER
INTERRUPT
Figure 5-15
Figure 5-14 CPU Space Address Encoding
FUNCTION
Freescale Semiconductor, Inc.
1 1 1
2
1 1 1
2
1 1 1
2
CODE
For More Information On This Product,
0
0
0
SYSTEM INTEGRATION MODULE
23
23
23
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Go to: www.freescale.com
for a flowchart of the breakpoint operation. Refer to the
ADDRESS BUS
CPU SPACE
TYPE FIELD
19
19
19
CPU SPACE CYCLES
16
16
16
4
BKPT#
LEVEL
2
1
T 0
0
0
0
1
CPU SPACE CYC TIM
5-41