MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 193

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

8.7.3 Sample Time
8.7.4 Resolution
8.7.5 Conversion Control Logic
M68HC16 Z SERIES
USER’S MANUAL
ADC clock speed must be between 0.5 MHz and 2.1 MHz. The reset value of the PRS
field is %00011, which divides a nominal 16.78 MHz system clock by eight, yielding
maximum ADC clock frequency. There are a minimum of four IMB clock cycles for
each ADC clock cycle.
The first two portions of all sample periods require four ADC clock cycles. During the
third portion of a sample period, the selected channel is connected directly to the RC
DAC array for a specified number of clock cycles. The value of the STS field in
ADCTL0 determines the number of cycles. Refer to
cycles required for a sample period is the value specified by STS plus four. Sample
time is determined by PRS value.
ADC resolution can be either eight or ten bits. Resolution is determined by the state of
the RES10 bit in ADCTL0. Both 8-bit and 10-bit conversion results are automatically
aligned in the result registers.
Analog-to-digital conversions are performed in sequences. Sequences are initiated by
any write to ADCTL1. If a conversion sequence is already in progress, a write to either
control register will abort it and reset the SCF and CCF flags in the A/D status register.
There are eight conversion modes. Conversion mode is determined by ADCTL1 con-
trol bits. Each conversion mode affects the bits in status register ADCSTAT differently.
Result storage differs from mode to mode.
PRS[4:0]
%00000
%00001
%00010
%00011
%11101
%11110
%11111
Freescale Semiconductor, Inc.
For More Information On This Product,
ANALOG-TO-DIGITAL CONVERTER
System Clock/60
System Clock/62
System Clock/64
System Clock/4
System Clock/6
System Clock/8
Table 8-4 TS Field Selection
Table 8-3 Prescaler Output
ADC Clock
STS[1:0]
Reserved
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00
01
10
11
16 A/D clock periods
2 A/D clock periods
4 A/D clock periods
8 A/D clock periods
System Clock
Sample Time
Minimum
30.0 MHz
31.0 MHz
32.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
—
Table
System Clock
8-4. The number of clock
Maximum
12.6 MHz
16.8 MHz
8.4 MHz
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—
—
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8-7