MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 425

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

HMIE — HALTA and MODF Interrupt Enable
HALT — Halt QSPI
SPIF — QSPI Finished Flag
MODF — Mode Fault Flag
HALTA — Halt Acknowledge Flag
Bit 4 — Not Implemented
CPTQP[3:0] — Completed Queue Pointer
D.6.14 Receive Data RAM
RR[0:F] — Receive Data RAM
M68HC16 Z SERIES
USER’S MANUAL
HMIE enables interrupt requests generated by the HALTA status flag or the MODF
status flag in SPSR.
When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state
from which it can later be restarted.
SPIF is set after execution of the command at the address in ENDQP[3:0].
The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the SS
input pin is negated by an external driver.
HALTA is set when the QSPI halts in response to setting the SPCR3 HALT bit.
CPTQP[3:0] points to the last command executed. It is updated when the current com-
mand is complete. When the first command in a queue is executing, CPTQP[3:0] con-
tains either the reset value $0 or a pointer to the last command completed in the
previous queue.
Data received by the QSPI is stored in this segment. The CPU16 reads this segment
to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the indi-
vidual queue entry. Receive RAM data can be accessed using byte, word, or long-
word addressing.
0 = HALTA and MODF interrupts disabled.
1 = HALTA and MODF interrupts enabled.
0 = QSPI operates normally.
1 = QSPI is halted for subsequent restart.
0 = QSPI is not finished.
1 = QSPI is finished.
0 = Normal operation.
1 = Another SPI node requested to become the network SPI master while the QSPI
0 = QSPI is not halted.
1 = QSPI is halted.
was enabled in master mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
REGISTER SUMMARY
$YFFD00 – $YFFD1F
D-51