MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 127

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.3.3 External Bus Clock
5.3.4 Low-Power Operation
M68HC16 Z SERIES
USER’S MANUAL
The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the E-
clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devic-
es and peripherals. ECLK frequency can be set to system clock frequency divided by
eight or system clock frequency divided by sixteen. The clock is enabled by the
CS10PA[1:0] field in chip-select pin assignment register 1 (CSPAR1). ECLK operation
during low-power stop is described in the following paragraph. Refer to
lects
Low-power operation is initiated by the CPU16. To reduce power consumption selec-
tively, the CPU can set the STOP bits in each module configuration register. To mini-
mize overall microcontroller power consumption, the CPU can execute the LPSTOP
instruction which causes the SIM to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are
turned off, but module registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of
the current interrupt mask into the clock control logic. The SIM brings the MCU out of
low-power stop mode when one of the following exceptions occur:
Refer to
During a low-power stop mode, unless the system clock signal is supplied by an ex-
ternal source and that source is removed, the SIM clock control logic and the SIM clock
signal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for
the RESET and IRQ pins are clocked by SIMCLK. The SIM can also continue to gen-
erate the CLKOUT signal while in low-power stop mode.
During low-power stop mode, the address bus continues to drive the LPSTOP instruc-
tion, and bus control signals are negated. I/O pins configured as outputs continue to
hold their previous state; I/O pins configured as inputs will be in a high-impedance
state.
STSIM and STEXT bits in SYNCR determine clock operation during low-power stop
mode.
The flowchart shown in
bits when MC68HC16Z1, MC68CK16Z1, MC68CM16Z1, MC68HC16Z2, and
MC68HC16Z3 MCUs enter normal low-power stop mode. Any clock in the off state is
held low. If the synthesizer VCO is turned off during low-power stop mode, there is a
PLL relock delay after the VCO is turned back on.
of the STSIM and STEXT bits when MC68HC16Z4 and MC68CK16Z4 MCUs enter
normal low-power stop mode.
• RESET
• Trace
• SIM interrupt of higher priority than the stored interrupt mask
for more information about the external bus clock.
5.6.4.2 LPSTOP Broadcast Cycle
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 5-6
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
summarizes the effects of the STSIM and STEXT
for more information.
Figure 5-7
summarizes the effects
5.9 Chip-Se-
5-21