MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 413

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

STOP — Low-Power Stop Mode Enable
FRZ1 — FREEZE Assertion Response
FRZ0 — Not Implemented
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted
Bits [6:4] — Not Implemented
IARB[3:0] — Interrupt Arbitration ID
D.6.2 QSM Test Register
QTEST — QSM Test Register
D.6.3 QSM Interrupt Level Register/Interrupt Vector Register
QILR — QSM Interrupt Levels Register
QIVR — QSM Interrupt Vector Register
M68HC16 Z SERIES
USER’S MANUAL
15
NOT USED
RESET:
When STOP is set, the QSM enters low-power stop mode. The system clock input to
the module is disabled. While STOP is set, only QSMCR reads and writes are guar-
anteed to be valid, but only writes to the QSPI RAM and other QSM registers are guar-
anteed valid. The SCI receiver and transmitter and the QSPI should be disabled
before STOP is set. To stop the QSPI, set the HALT bit in SPCR3, wait until the HAL-
TA flag is set, then set STOP. To stop the SCI, clear the TS and RE bits in SCCR1.
FRZ1 determines what action is taken by the QSPI when the IMB FREEZE signal is
asserted.
This bit has no effect because the CPU16 in the MCU operates only in supervisor
mode.
The IARB field is used to arbitrate between simultaneous interrupt requests of the
same priority. Each module that can generate interrupt requests must be assigned a
unique, non-zero IARB field value in order to request an interrupt.
Used for factory test only.
The values of ILQSPI[2:0] and ILSCI[2:0] in QILR determine the priority of QSPI and
SCI interrupt requests. QIVR determines the value of the interrupt vector number the
QSM supplies when it responds to an interrupt acknowledge cycle.
0 = QSM clock operates normally.
1 = QSM clock is stopped.
0 = Ignore the IMB FREEZE signal.
1 = Halt the QSPI on a transfer boundary.
14
13
0
ILQSPI[2:0]
12
0
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
10
0
Go to: www.freescale.com
ILSCI[2:0]
REGISTER SUMMARY
9
0
8
0
7
0
6
0
5
0
4
0
INTV[7:0]
3
1
2
1
$YFFC02
$YFFC04
$YFFC05
1
1
D-39
0
1