MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 214

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

9.2.2 QSM Pin Control Registers
9-4
The QSM uses nine pins. Eight of the pins can be used for serial communication or for
parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns
the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI.
The port QS data direction register (DDRQS) determines whether pins are inputs or
outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the
pin an output. DDRQS affects both QSPI function and I/O function. DDQS7 deter-
mines the direction of the TXD pin only when the SCI transmitter is disabled. When the
SCI transmitter is enabled, the TXD pin is an output.
The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins de-
fined as outputs. PORTQS reads return data present on the pins. To avoid driving un-
defined data, first write PORTQS, then configure DDRQS.
PQSPAR and DDRQS are 8-bit registers located at the same word address. Refer to
Table 9-1
NOTES:
PCS0/SS
QSM Pin
PCS[1:3]
MISO
MOSI
SCK
TXD
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which case it
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE set in SCCR1), in
RXD
for a summary of QSM pin functions.
becomes the QSPI serial clock SCK.
which case it becomes the SCI serial data output TXD.
2
1
Table 9-1 Effect of DDRQS on QSM Pin Function
QSPI Mode
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Freescale Semiconductor, Inc.
—
—
For More Information On This Product,
DDRQS Bit
DDQS[4:6]
QUEUED SERIAL MODULE
Go to: www.freescale.com
DDQS0
DDQS1
DDQS2
DDQS3
DDQS7
None
Bit State
NA
—
—
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Serial data output from QSPI
Serial data output from QSPI
Assertion causes mode fault
Serial data output from SCI
Disables chip-select output
Disables slave select input
Serial data input to QSPI
Serial data input to QSPI
Clock output from QSPI
QSPI slave select input
Serial data input to SCI
Disables data output
Disables data output
Clock input to QSPI
Disables data input
Disables data input
Chip-select output
Chip-select output
Pin Function
Inactive
Inactive
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