MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 132

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5-26
Both writes must occur before time-out in the order listed. Any number of instructions
can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the
software watchdog timing (SWT[1:0]) field in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be select-
ed. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in
SWT[1:0] selects the divide ratio used to establish the software watchdog time-out
period.
The following equation calculates the time-out period for a slow reference frequency,
where f
The following equation calculates the time-out period for a fast reference frequency,
where f
The following equation calculates the time-out period for an externally input clock fre-
quency on both slow and fast reference frequency devices, when f
system clock frequency.
Table 5-10
When SWT[1:0] are modified, a watchdog service sequence must be performed be-
fore the new time-out period can take effect.
ref
ref
Time-Out Period
Table
is equal to the EXTAL crystal frequency.
is equal to the EXTAL crystal frequency.
Time-Out Period
Time-Out Period
shows the divide ratio for each combination of SWP and SWT[1:0] bits.
Table 5-9 MODCLK Pin and SWP Bit During Reset
5-9. System software can change SWP value.
Freescale Semiconductor, Inc.
For More Information On This Product,
=
SYSTEM INTEGRATION MODULE
0 (External Clock)
1 (Internal Clock)
------------------------------------------------------------------------------------------------------------------------------- ------------ -
128 Divide Ratio Specified by SWP and SWT[1:0]
=
=
Go to: www.freescale.com
MODCLK
Divide Ratio Specified by SWP and SWT[1:0]
----------------------------------------------------------------------------------------------------------------------- -
Divide Ratio Specified by SWP and SWT[1:0]
----------------------------------------------------------------------------------------------------------------------- -
1 ( 512)
0 ( 1)
SWP
f
f
f
sys
ref
ref
sys
M68HC16 Z SERIES
USER’S MANUAL
is equal to the