PIC18F24J10-I/ML Microchip Technology, PIC18F24J10-I/ML Datasheet - Page 81

• Manufacturer Part Number: PIC18F24J10-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F24J10-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1024Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Interface: I2C, SPI, USART
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
© 2009 Microchip Technology Inc.
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Name
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIE
OSCFIF
Bit 7
—
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
CMIP
CMIE
CMIF
Bit 6
—
—
bit 21
Bit 5
—
—
—
—
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INT0IE
FREE
Bit 4
—
—
—
WRERR
BCL1IP
BCL1IF
BCL1IE
RBIE
PIC18F45J10 FAMILY
Bit 3
7.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 21.0 “Special Features of the
CPU” for more detail.
7.6
See Section 21.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TMR0IF
Flash Program Operation During
Code Protection
WREN
Bit 2
—
—
—
PROTECTION AGAINST
SPURIOUS WRITES
INT0IF
Bit 1
WR
—
—
—
CCP2IP
CCP2IF
CCP2IE
RBIF
Bit 0
—
DS39682E-page 79
Values on
Reset
page
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