PIC18F24J10-I/ML Microchip Technology, PIC18F24J10-I/ML Datasheet - Page 335

• Manufacturer Part Number: PIC18F24J10-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F24J10-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1024Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Interface: I2C, SPI, USART
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

FIGURE 24-18:
TABLE 24-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 24-19:
TABLE 24-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
© 2009 Microchip Technology Inc.
120
121
122
Param.
125
126
Param
No.
No.
Note:
RX/DT
TX/CK
T
T
T
Note:
T
T
CK
CKRF
Symbol
DTRF
RX/DT
TX/CK
CK
Symbol
DT
pin
pin
H2
L2
V2
pin
pin
DT
DTL
CKL
Refer to Figure 24-3 for load conditions.
V SYNC XMIT (MASTER and SLAVE)
Refer to Figure 24-3 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
SYNC RCV (MASTER and SLAVE)
Data Hold before CK ↓ (DT hold time)
Data Hold after CK ↓ (DT hold time)
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
121
PIC18F45J10 FAMILY
126
Min
10
15
Min
Max
—
—
—
—
—
122
Units
Max
ns
ns
40
20
20
Units
ns
ns
ns
DS39682E-page 333
Conditions
Conditions