PIC18F24J10-I/ML Microchip Technology, PIC18F24J10-I/ML Datasheet
PIC18F24J10-I/ML
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PIC18F24J10-I/ML Summary of contents
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... Microchip Technology Inc. PIC18F45J10 Family 28/40/44-Pin High-Performance, RISC Microcontrollers Data Sheet DS39682E ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Internal 31 kHz Oscillator • Secondary Oscillator using Timer1 @ 32 kHz • Two-Speed Oscillator Start-up • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops Program Memory Device Flash # Single-Word (bytes) Instructions PIC18F24J10 16K 8192 PIC18F25J10 32K 16384 PIC18F44J10 16K 8192 PIC18F45J10 32K 16384 © ...
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... REF + CAP -/CV 1 REF 21 + REF CAP 19 PIC18F24J10 4 18 PIC18F25J10 Pins are up to 5.5V tolerant RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/T0CKI/C1OUT RB4/KBI0/AN11 RB3/AN9/CCP2* RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO1 RC4/SDI1/SDA1 = Pins are up to 5.5V tolerant RB3/AN9/CCP2* RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT © 2009 Microchip Technology Inc. ...
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... Pin feature is dependent on device configuration. . (1) 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 * Pin feature is dependent on device configuration. Note 1: For the QFN package recommended that the bottom pad be connected to V © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY VREF REF 5 36 CAP 6 ...
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... TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2* * Pin feature is dependent on device configuration. DS39682E-page 4 = Pins are up to 5.5V tolerant RC0/T1OSO/T1CKI 2 OSC2/CLKO OSC1/CLKI PIC18F44J10 PIC18F45J10 27 RE2/CS/AN7 7 26 RE1/WR/AN6 8 25 RE0/RD/AN5 9 24 RA5/AN4/SS1/C2OUT DDCORE /V CAP © 2009 Microchip Technology Inc. ...
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... Appendix A: Revision History............................................................................................................................................................. 349 Appendix B: Migration Between High-End Device Families............................................................................................................... 350 Index .................................................................................................................................................................................................. 353 The Microchip Web Site ..................................................................................................................................................................... 363 Customer Change Notification Service .............................................................................................................................................. 363 Customer Support .............................................................................................................................................................................. 363 Reader Response .............................................................................................................................................................................. 364 PIC18F45J10 family Product Identification System ........................................................................................................................... 365 © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY DS39682E-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39682E-page 6 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F24J10 • PIC18LF24J10 • PIC18F25J10 • PIC18LF25J10 • PIC18F44J10 • PIC18LF44J10 • PIC18F45J10 • PIC18LF45J10 This family offers the advantages of all PIC18 microcontrollers – namely, high computational perfor- mance at an economical price ...
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... Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory (16 Kbytes PIC18F24J10/44J10 devices and 32 Kbytes for PIC18F25J10/45J10). 2. A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices). 3. I/O ports (3 bidirectional ports on 28-pin devices, 5 bidirectional ports on 40/44-pin devices). ...
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... TABLE 1-1: DEVICE FEATURES Features PIC18F24J10 Operating Frequency DC – 40 MHz Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Ports Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/PWM Modules Serial Communications Enhanced USART Parallel Communications (PSP) 10-Bit Analog-to-Digital Module 10 Input Channels ...
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... PIC18F45J10 FAMILY FIGURE 1-1: PIC18F24J10/25J10 (28-PIN) BLOCK DIAGRAM Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (16/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine Instruction Control Signals ...
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... Timer0 Comparator ECCP1 CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. Note 1: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices. 2: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Data Bus<8> Data Latch 8 Data Memory (3.9 Kbytes) Address Latch ...
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... PIC18F45J10 FAMILY TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS Pin Number SPDIP, Pin Name SOIC, QFN SSOP MCLR 1 26 MCLR OSC1/CLKI 9 6 OSC1 CLKI OSC2/CLKO 10 7 OSC2 CLKO Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. ...
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... TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2/V -/ REF REF RA2 AN2 V - REF CV REF RA3/AN3 REF RA3 AN3 V + REF RA5/AN4/SS1/C2OUT 7 4 RA5 AN4 SS1 C2OUT ...
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... PIC18F45J10 FAMILY TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RB0/INT0/FLT0/AN12 21 18 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 22 19 RB1 INT1 AN10 RB2/INT2/AN8 23 20 RB2 INT2 AN8 RB3/AN9/CCP2 24 21 RB3 AN9 (1) CCP2 RB4/KBI0/AN11 25 22 RB4 ...
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... TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RC0/T1OSO/T1CKI 11 8 RC0 T1OSO T1CKI RC1/T1OSI/CCP2 12 9 RC1 T1OSI (2) CCP2 RC2/CCP1 13 10 RC2 CCP1 RC3/SCK1/SCL1 14 11 RC3 SCK1 SCL1 RC4/SDI1/SDA1 15 12 RC4 SDI1 SDA1 RC5/SDO1 16 13 ...
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... Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP™ programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... Enhanced CCP1 output. 4 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. 5 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... PIC18F45J10 FAMILY NOTES: DS39682E-page 22 © 2009 Microchip Technology Inc. ...
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... REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 2- MCLR C1 V (2) C6 ...
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... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXJXX JP C1 and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. ...
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... Frequency (MHz) Data for Murata GRM21BF50J106ZE01 shown. Note: Measurements at 25° bias. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor to V output to logic low. Devices” SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT unused pins and drive the SS © 2009 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a fre- Note: quency out of the crystal manufacturer’s specifications. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 3-1: ( Output (1) C2 Note 1: See Table 3-1 and Table 3-2 for initial values of C1 and C2 ...
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... OSC1 pin in the HS mode, as shown in Figure 3-3. In this configuration, the divide-by-4 output on OSC2 is not available. FIGURE 3-3: Clock from of external Ext. System EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18F45J10 OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18F45J10 (HS Mode) Open OSC2 © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads Note 1: as ‘0’. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 3-4: PLL BLOCK DIAGRAM HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) ...
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... Features of the CPU” for Configuration register details. PIC18F45J10 Family HS, EC HSPLL, ECPLL 4 x PLL T1OSC Internal Oscillator INTRC Source FOSC<2:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2009 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> ...
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... It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 3.6.1.1 System Clock Selection and the FOSC2 Configuration Bit The SCS bits are cleared on all forms of Reset. In the device’ ...
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... MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption Section 24.2 “DC Characteristics: Power-Down and Supply Current”. © 2009 Microchip Technology Inc. R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown ...
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... Feedback inverter disabled at quiescent voltage level See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset. Note: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes) ...
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... PIC18F45J10 FAMILY NOTES: DS39682E-page 34 © 2009 Microchip Technology Inc. ...
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... RC_IDLE 1 11 IDLEN reflects its value when the SLEEP instruction is executed. Note 1: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • the primary clock, as defined by the FOSC<1:0> ...
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... Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run n-1 n Clock Transition © 2009 Microchip Technology Inc. ...
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... Note 1024 T . These intervals are not shown to scale. OST OSC © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-3) ...
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... RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits OSTS bit Set CSD © 2009 Microchip Technology Inc. ...
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... OSC1 CPU Clock Peripheral Clock Program Counter Wake Event © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS< ...
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... T CSD is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. (see Section 4.2 “Run , following the wake event ...
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... PWRT 11-Bit Ripple Counter INTRC Note 1: The Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower six bits of the register indicate that a specific Reset event has occurred ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39682E-page 42 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... BOR running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises above V , the Power-up Timer will execute the BOR additional time delay. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 5- Note 1: External Power-on Reset circuit is required ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 5-5). This is useful for testing purposes synchronize more than one PIC18F device operating in parallel PWRT © 2009 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ...
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... FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY T PWRT T PWRT , V RISE > 3. PWRT ): CASE 1 ...
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... Reset. Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( POR STKPTR Register (2) BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt 2: vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for Reset value for specific condition. 4: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt 2: vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 3: See Table 5-1 for Reset value for specific condition. 4: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset ...
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... Interrupt uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu --u- uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --u- uuuu © 2009 Microchip Technology Inc. ...
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... NOP instruction). The PIC18F24J10 and PIC18F44J10 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The PIC18F25J10 and PIC18F45J10 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions ...
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... Additional details on the device Configuration Words are provided in Section 21.1 “Configuration Bits”. TABLE 6-1: FLASH CONFIGURATION WORD FOR PIC18F45J10 FAMILY DEVICES Program Configuration Device Memory (Kbytes) PIC18F24J10 16 3FF8h to 3FFFh PIC18F44J10 PIC18F25J10 32 7FF8h to 7FFFh PIC18F45J10 © 2009 Microchip Technology Inc. through Word ...
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... Top-of-Stack Registers TOSU TOSH 00h 1Ah © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of- stack Special Function Registers ...
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... Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP2 SP1 SP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SUB1 • RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The CALL and GOTO instructions have the absolute pro- gram memory address embedded into the instruction. Since instructions are always stored on word boundar- ies, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. ...
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... Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. (2) From Opcode © 2009 Microchip Technology Inc. ...
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... Unimplemented registers are read as ‘0’. 2: This register is not available in 28-pin devices. 3: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the periph- eral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU’ ...
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... PIC18F45J10 FAMILY TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF — PCLATU — — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC< ...
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... TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN — — WDTCON — — — RCON IPEN — CM TMR1H Timer1 Register High Byte ...
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... PIC18F45J10 FAMILY TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte RCREG EUSART Receive Register TXREG EUSART Transmit Register TXSTA CSRC TX9 ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the bits in the STATUS register ...
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... Example 6-5. EXAMPLE 6-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2009 Microchip Technology Inc. ...
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... In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “ ...
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... Figure 6-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 22.2.1 “Extended Instruction Syntax”. © 2009 Microchip Technology Inc. ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 000h 060h 080h Bank 0 100h Bank 1 ...
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... These instructions are executed as described in Section 22.2 “Extended Instruction Set”. Bank 0 Bank 0 Bank 1 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory 00h Bank 1 “Window” 5Fh Bank 0 7Fh 80h SFRs FFh Access Bank © 2009 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Reading Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... Initiates a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-x R/W-0 FREE ...
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... Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 Table Erase TBLPTR<20:10> Table Write TBLPTR<20:6> Table Read – TBLPTR<21:0> TBLPTRL 0 Table Write TBLPTR<5:0> © 2009 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... The CPU will stall for duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
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... Set the EECON1 register for the write operation: • set WREN to enable byte writes. 4. Disable interrupts. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
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... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block © 2009 Microchip Technology Inc. ...
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... OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 7.5.4 PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 21.0 “ ...
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... PIC18F45J10 FAMILY NOTES: DS39682E-page 80 © 2009 Microchip Technology Inc. ...
Page 83
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
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... PIC18F45J10 FAMILY FIGURE 9-1: PIC18F24J10/25J10/44J10/45J10 INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3, 0> PIE2<7:6, 3, 0> IPR2<7:6, 3, 0> PIR3<7:6> PIE3<7:6> IPR3<7:6> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3, 0> PIE2<7:6, 3, 0> IPR2<7:6, 3, 0> PIR3<7:6> PIE3<7:6> IPR3<7:6> DS39682E-page 84 TMR0IF TMR0IE TMR0IP ...
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... None of the RB<7:4> pins have changed state A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and Note 1: allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Interrupt flag bits are set when an interrupt Note: ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39682E-page 86 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 89
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 ...
Page 90
... R-0 R/W-0 R/W-0 TXIF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... The transmission/reception is complete (must be cleared in software Waiting to transmit/receive bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module bus collision occurred (must be cleared in software bus collision occurred bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 R/W-0 U-0 — BCLIF — ...
Page 92
... Disables the TMR1 overflow interrupt This bit is not implemented on 28-pin devices and should be read as ‘0’. Note 1: DS39682E-page 90 R/W-0 R/W-0 R/W-0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module Enabled 0 = Disabled bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 R/W-0 U-0 — BCL1IE — Unimplemented bit, read as ‘0’ ...
Page 94
... Low priority This bit is not implemented on 28-pin devices and should be read as ‘0’. Note 1: DS39682E-page 92 R/W-1 R/W-1 R/W-1 TXIP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module High priority 0 = Low priority bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 R/W-1 U-0 — BCL1IP — Unimplemented bit, read as ‘0’ ...
Page 96
... For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. DS39682E-page 94 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → ...
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... PIC18F45J10 FAMILY NOTES: DS39682E-page 96 © 2009 Microchip Technology Inc. ...
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... TRIS Latch RD TRIS PORT © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
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... MOVLW 07h ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs © 2009 Microchip Technology Inc. ...
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... DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output; Legend Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY I/O I/O ...
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... RA5 — RA3 RA2 TRISA5 — TRISA3 TRISA2 VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 CVRR CVRSS CVR3 CVR2 Reset Bit 1 Bit 0 Values on page RA1 RA0 50 50 TRISA1 TRISA0 50 PCFG1 PCFG0 48 CM1 CM0 49 CVR1 CVR0 49 © 2009 Microchip Technology Inc. ...
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... Note: configured as analog inputs by default and read as ‘0’; RB<7:5> are configured as digital inputs. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Four of the PORTB pins (RB<7:4>) have an interrupt- on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin configured as an output is excluded from the interrupt- on-change comparison). The input pins (of RB< ...
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... PORTB<7> data input; weak pull-up when RBPU bit is cleared. I TTL Interrupt-on-change pin. O DIG Serial execution data output for ICSP and ICD operation Serial execution data input for ICSP and ICD operation. Description (1) (1) (1) (1) (1) (3) (3) (3) © 2009 Microchip Technology Inc. ...
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... GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE ...
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... EXAMPLE 10-4: INITIALIZING PORTC CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches CLRF LATC ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs © 2009 Microchip Technology Inc. ...
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... C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3. Note 1: Enhanced PWM output is available only on PIC18F44J10/45J10 devices. 2: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY I/O I/O Type ...
Page 108
... PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register DS39682E-page 106 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset Bit 1 Bit 0 Values on page RC1 RC0 © 2009 Microchip Technology Inc. ...
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... Capture/Compare/PWM (ECCP) Module” Power-on Reset, these pins are Note: configured as digital inputs. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.7 “ ...
Page 110
... PSP read data output (LATD<7>); takes priority over port data. TTL PSP write data input. DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events C™/SMB = I C/SMBus input buffer; © 2009 Microchip Technology Inc. ...
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... OBF (1) (1) CCP1CON P1M1 P1M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. These registers and/or bits are not available in 28-pin devices. Note 1: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 ...
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... CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 0Ah ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 03h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs © 2009 Microchip Technology Inc. ...
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... Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 U-0 R/W-1 PSPMODE — TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 ...
Page 114
... RE2 — — — PORTE Data Latch Register (Read and Write to Data Latch) IBOV PSPMODE — TRISE2 VCFG1 VCFG0 PCFG3 PCFG2 Description Reset Bit 1 Bit 0 Values on page RE1 RE0 50 50 TRISE1 TRISE0 50 PCFG1 PCFG0 48 © 2009 Microchip Technology Inc. ...
Page 115
... PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The timing for the control signals in Write and Read modes is shown in Figure 10-4 and Figure 10-5, respectively ...
Page 116
... SSP1IF CCP1IF RCIE TXIE SSP1IE CCP1IE RCIP TXIP SSP1IP CCP1IP VCFG1 VCFG0 PCFG3 PCFG2 Reset Bit 1 Bit 0 Values on page RD1 RD0 RE1 RE0 50 50 TRISE1 TRISE0 50 INT0IF RBIF 47 TMR2IF TMR1IF 49 TMR2IE TMR1IE 49 TMR2IP TMR1IP 49 PCFG1 PCFG0 48 © 2009 Microchip Technology Inc. ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 118
... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TMR0ON T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F45J10 FAMILY NOTES: DS39682E-page 118 © 2009 Microchip Technology Inc. ...
Page 121
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... TRISC<1:0> are ignored and the pins are read as ‘0’. Timer1 Clock Input On/Off 1 Prescaler F /4 OSC Internal 0 Clock 2 TMR1CS Clear TMR1 TMR1L (CCP Special Event Trigger) 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow © 2009 Microchip Technology Inc. ...
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... All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Timer1 Clock Input 1 Prescaler ...
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... Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING OSC1 OSC2 RC0 RC1 RC2 © 2009 Microchip Technology Inc. ...
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... The Special Event Triggers from the Note: ECCP1/CCPx module will not set the TMR1IF interrupt flag bit (PIR1<0>). © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 12.6 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 12.3 “Timer1 Oscillator” ...
Page 126
... Reset hours ; Done Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF RCIF TXIF SSP1IF CCP1IF RCIE TXIE SSP1IE CCP1IE RCIP TXIP SSP1IP CCP1IP Reset Bit 1 Bit 0 Values on page INT0IF RBIF 47 TMR2IF TMR1IF 49 TMR2IE TMR1IE 49 TMR2IP TMR1IP TMR1CS TMR1ON 48 © 2009 Microchip Technology Inc. ...
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... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSP1IF CCP1IF TXIE SSP1IE CCP1IE TXIP SSP1IP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 47 TMR2IF TMR1IF 49 TMR2IE TMR1IE 49 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
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... CCPx pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set) 11xx = PWM mode © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules ...
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... Changing the pin assignment of CCP2 does not auto- matically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation regardless of where it is located. Interaction © 2009 Microchip Technology Inc. and ...
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... Prescaler ÷ CCP1CON<3:0> CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 14.2.3 CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared ...
Page 132
... Reset) Set CCP1IF Output Compare Logic Match 4 CCP1CON<3:0> Special Event Trigger (Timer1 Reset, A/D Trigger) Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2009 Microchip Technology Inc. ...
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... CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1. These bits are not implemented on 28-pin devices and should be read as ‘0’. Note 1: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE ...
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... CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2009 Microchip Technology Inc. ...
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... CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 15.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY EQUATION 14-3: PWM Resolution (max) If the PWM duty cycle value is longer than ...
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... CCP2M2 PSSAC1 PSSAC0 PSSBD1 (1) (1) (1) PDC5 PDC4 PDC3 PDC2 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 47 PD POR BOR 46 TMR2IF TMR1IF 49 TMR2IE TMR1IE 49 TMR2IP TMR1IP CCP1M1 CCP1M0 CCP2M1 CCP2M0 49 (1) (1) PSSBD0 49 (1) (1) (1) PDC1 PDC0 49 © 2009 Microchip Technology Inc. ...
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... ECCP module are the same as described for the standard CCP module. The control register for the Enhanced CCP module is shown in Register 15-1. It differs from the CCP1CON ECCP1 is register in PIC18F24J10/25J10 devices in that the two Most Significant bits are implemented to control PWM functionality. R/W-0 R/W-0 R/W-0 ...
Page 138
... PWM. provided in and Timer RC2 RD5 All 40/44-pin Devices: CCP1 RD5/PSP5 P1A P1B P1A P1B and Section 14.3 “Compare or for PWM Operation” RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2009 Microchip Technology Inc. ...
Page 139
... CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
Page 140
... The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 15-2. ) bits 9.77 kHz 39.06 kHz FFh FFh 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
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... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Dead-band delay is programmed using the ECCP1DEL register (see Section 15.4.6 “Programmable Note 1: Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 0 Duty Cycle Period (1) Delay (1) Delay ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2009 Microchip Technology Inc. ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. Note © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 144
... Reduce PWM for a PWM period before bits changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2009 Microchip Technology Inc. ...
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... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals ...
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... R/W-0 R/W-0 (1) (1) (1) PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( cycles, between the scheduled and actual time for a PWM OSC OSC R/W-0 R/W-0 R/W-0 (1) (1) (1) PDC2 PDC1 PDC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 147
... PSSBD<1:0>: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Reserved on 28-pin devices; maintain these bits clear. Note 1: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 R/W-0 ECCPAS0 ...
Page 148
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Resumes ECCPASE Cleared by Firmware PWM Resumes © 2009 Microchip Technology Inc. ...
Page 149
... Wait until TMRx overflows (TMRxIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled ...
Page 150
... Bit 1 Bit 0 Values on page INT0IF RBIF 47 PD POR BOR 46 TMR2IF TMR1IF 49 TMR2IE TMR1IE 49 TMR2IP TMR1IP 49 — — CCP2IF 49 — — CCP2IE 49 — — CCP2IP TMR1CS TMR1ON CCP1M1 CCP1M0 49 (1) (1) PSSBD1 PSSBD0 49 (1) (1) (1) PDC2 PDC1 PDC0 49 © 2009 Microchip Technology Inc. ...
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... C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode PIC18F24J10/25J10 (28-pin) devices have one MSSP module designated as MSSP1. PIC18F44J10/45J10 (40/44-pin) devices have two MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. ...
Page 152
... SSPxBUF and the SSPxIF interrupt is set. During transmission, double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) the SSPxBUF is not R-0 R bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by Note 1: writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. 2: Bit combinations not specifically listed here are either reserved or implemented © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 (2) (3) CKP ...
Page 154
... Example 16-1 shows the loading of the SSP1BUF (SSP1SR) transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions. © 2009 Microchip Technology Inc. completed for data ...
Page 155
... Serial Input Buffer (SSPxBUF) Shift Register (SSPxSR) MSb LSb PROCESSOR 1 © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 16.3.4 TYPICAL CONNECTION Figure 16-2 shows a typical connection between two microcontrollers ...
Page 156
... SMP bit. The time when the SSPxBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...
Page 157
... SSPxIF Interrupt Flag SSPxSR to SSPxBUF © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application ...
Page 158
... Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF DS39682E-page 156 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 3 bit bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...
Page 159
... EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 16.3.10 BUS MODE COMPATIBILITY Table 16-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...
Page 160
... R/W SSPEN CKP SSPM3 SSPM2 D R/W Reset Bit 1 Bit 0 Values on page INT0IF RBIF 47 TMR2IF TMR1IF 49 TMR2IE TMR1IE 49 TMR2IP TMR1IP 49 — — 49 — — 49 — — 49 TRISA1 TRISA0 50 TRISC1 TRISC0 50 TRISD1 TRISD0 50 48 SSPM1 SSPM0 SSPM1 SSPM0 © 2009 Microchip Technology Inc. ...
Page 161
... Stop bit Detect Only port I/O names are used in this diagram for Note: the sake of brevity. Refer to the text for a full list of multiplexed functions. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 16.4.1 REGISTERS The MSSP module has six registers for I These are: • ...
Page 162
... ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. 3: DS39682E-page 160 2 C™ MODE) R-0 R-0 R-0 ( Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C mode only) © 2009 Microchip Technology Inc bit Bit is unknown ...
Page 163
... C Slave mode, 10-bit address 2 0110 = I C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. When enabled, the SDAx and SCLx pins must be configured as inputs. Note 1: © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 2 R/W-0 R/W-0 (1) CKP ...
Page 164
... SSPxBUF are disabled). DS39682E-page 162 2 R/W-0 R/W-0 (1) (2) (2) ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) ( (2) (2) (2) C™ MASTER MODE) R/W-0 R/W-0 R/W-0 (2) (2) (2) RSEN SEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 165
... Clock stretching is enabled for both slave transmit and slave receive (stretch enabled Clock stretching is disabled 2 If the I C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or Note 1: writes to the SSPxBUF are disabled). © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 2 R/W-0 R/W-0 ADMSK4 ADMSK3 ADMSK2 U = Unimplemented bit, read as ‘ ...
Page 166
... Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits, SSPxIF and BF, are set). 9. Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. © 2009 Microchip Technology Inc. ...
Page 167
... ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY For the module to issue an address Acknowledge sufficient to match only on addresses that do not have an active address mask. In 10-Bit Addressing mode, ADMSK< ...
Page 168
... CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. © 2009 Microchip Technology Inc. ...
Page 169
... FIGURE 16-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING) © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY DS39682E-page 167 ...
Page 170
... PIC18F45J10 FAMILY 2 FIGURE 16-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING) DS39682E-page 168 © 2009 Microchip Technology Inc. ...
Page 171
... FIGURE 16-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING) © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY DS39682E-page 169 ...
Page 172
... PIC18F45J10 FAMILY 2 FIGURE 16-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING) DS39682E-page 170 © 2009 Microchip Technology Inc. ...
Page 173
... SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 16.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode ...
Page 174
... I C bus have deasserted SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 16-12). Master Device Asserts Clock Master Device Deasserts Clock DX – 1 © 2009 Microchip Technology Inc. ...
Page 175
... FIGURE 16-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING) © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY DS39682E-page 173 ...
Page 176
... PIC18F45J10 FAMILY 2 FIGURE 16-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING) DS39682E-page 174 © 2009 Microchip Technology Inc. ...
Page 177
... S SSPxIF BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) GCEN (SSPxCON2<7>) © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. ...
Page 178
... Start bit, Stop bit, Acknowledge Generate Start bit Detect, Stop bit Detect, Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1); Write Collision Detect, Clock Arbitration, Set SSPxIF, BCLxIF; State Counter for Reset ACKSTAT, PEN (SSPxCON2) End of XMIT/RCV SSPM<3:0> SSPxADD<6:0> Baud Rate Generator © 2009 Microchip Technology Inc. ...
Page 179
... SCLx clock frequency for 2 either 100 kHz, 400 kHz or 1 MHz I C operation. See Section 16.4.7 “Baud Rate” for more detail. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY A typical transmit sequence would go as follows: 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPxCON2< ...
Page 180
... MHz 09h 2 MHz 00h 2 C specification (which applies to rates greater than 2 C Master mode OSC F SCL (2 Rollovers of BRG) (1) 400 kHz 312.5 kHz 100 kHz (1) 400 kHz 308 kHz 100 kHz (1) 333 kHz 100 kHz (1) 1 MHz © 2009 Microchip Technology Inc. ...
Page 181
... BRG 03h Value BRG Reload © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 16-18) ...
Page 182
... SSPxCON2 is disabled until the Start condition is complete. Set S bit (SSPxSTAT<3>) SDAx = 1, At completion of Start bit, SCLx = 1 hardware clears SEN bit and sets SSPxIF bit T T BRG BRG Write to SSPxBUF occurs here 1st bit T BRG T BRG S 2nd bit © 2009 Microchip Technology Inc. ...
Page 183
... SDAx RSEN bit set by hardware on falling edge of ninth clock, end of Xmit SCLx © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Note 1: If RSEN is programmed while any other event is in progress, it will not take effect bus collision during the Repeated Start 2 ...
Page 184
... WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). CY © 2009 Microchip Technology Inc. ...
Page 185
... FIGURE 16-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESSING) © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY DS39682E-page 183 ...
Page 186
... PIC18F45J10 FAMILY 2 FIGURE 16-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING) DS39682E-page 184 © 2009 Microchip Technology Inc. ...
Page 187
... SSPxIF SSPxIF set at the end of receive Note one Baud Rate Generator period. BRG © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY 16.4.13 STOP CONDITION TIMING A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a ...
Page 188
... Control of the I be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. BRG 2 C port to its Idle state (Figure 16-25 bus bus can © 2009 Microchip Technology Inc. C ...
Page 189
... FIGURE 16-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx SCLx BCLxIF © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY Sample SDAx. While SCLx is high, SDAx line pulled low data doesn’t match what is driven by another source by the master. ...
Page 190
... Repeated loaded from Start or Stop conditions. SEN cleared automatically because of bus collision. MSSP module reset into Idle state. SSPxIF and BCLxIF are cleared in software SSPxIF and BCLxIF are cleared in software © 2009 Microchip Technology Inc. ...
Page 191
... BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION Less than T SDAx pulled low by other master. SDAx Reset BRG and assert SDAx. SCLx SEN BCLxIF S SSPxIF © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY SDAx = 0, SCLx = BRG BRG SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SDAx = 0, SCLx = 1 ...
Page 192
... SCLx pin is driven low and the Repeated Start condition is complete. Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. Cleared in software T T BRG BRG Interrupt cleared in software © 2009 Microchip Technology Inc. ‘0’ ‘0’ ‘0’ ...
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... SDAx Assert SDAx SCLx PEN BCLxIF P SSPxIF © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled ...
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... CCP2IE 49 — — CCP2IP 49 — — — 49 — — — 49 — — — 49 TRISC1 TRISC0 50 TRISD1 TRISD0 SSPM1 SSPM0 48 RSEN SEN 48 (2) (2) ADMSK1 SEN SSPM1 SSPM0 50 RSEN SEN 50 (2) (2) ADMSK1 SEN C™ mode Slave mode. See © 2009 Microchip Technology Inc. ...
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... Synchronous – Master (half duplex) with selectable clock polarity • Synchronous – Slave (half duplex) with selectable clock polarity © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/ EUSART: • ...
Page 196
... Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode. Note 1: DS39682E-page 194 R/W-0 R/W-0 (1) SYNC SENDB U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN overrun error bit 0 RX9D: 9th Bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 R-0 CREN ...
Page 198
... Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39682E-page 196 R/W-0 R/W-0 U-0 SCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Legend Don’t care value of SPBRGH:SPBRG register pair © 2009 Microchip Technology Inc. PIC18F45J10 FAMILY advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared) ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39682E-page 198 Bit 5 Bit 4 Bit 3 Bit 2 TXEN SYNC SENDB BRGH SREN CREN ADDEN FERR — SCKP BRG16 — Reset Values Bit 1 Bit 0 on page TRMT TX9D 49 OERR RX9D 49 WUE ABDEN © 2009 Microchip Technology Inc. ...