ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 95

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ZLP128ICE01ZEM

Manufacturer Part Number
ZLP128ICE01ZEM
Description
EMULATOR CRIMZON Z8 ZLP12840
Manufacturer
Zilog

Specifications of ZLP128ICE01ZEM

Interface Type
RS-232, Ethernet, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3829
Table 43. Interrupt Priority Register (IPR)
PS024410-0108
Bit
Field
Reset
R/W
Address
Bit
Position Value Description
[7:6]
[5]
{[4:3], [0]}
[2]
[1]
Interrupt Priority Register
000
001
010
011
100
101
110
111
0
1
0
1
0
1
Reserved
X
7
The Interrupt Priority Register
priority. Interrupts are divided into three groups of two—Group A, Group B, and Group C.
IPR bits 4, 3, and 0 determine which interrupt group has priority. For example, if interrupts
IRQ5, IRQ1, and IRQ0 occur simultaneously when IPR[4:3, 0]=001b, the interrupts are
serviced in the following order: IRQ1, IRQ0, and IRQ5.
IPR bits 5, 2, and 1 determine which interrupt within each group has higher priority.
Reserved
Reads are undefined; writes must be 00b.
Group A Priority (IRQ3, IRQ5)
IRQ5 > IRQ3
IRQ3 > IRQ5
Group Priority
Reserved
C > A > B
A > B > C
A > C > B
B > C > A
C > B > A
B > A > C
Reserved
Group B Priority (IRQ0, IRQ2)
IRQ2 > IRQ0
IRQ0 > IRQ2
Group C Priority (IRQ1, IRQ4)
IRQ1 > IRQ4
IRQ4 > IRQ1
X
6
Group A
Priority
W
X
5
Bank Independent: F9h; Linear: 0F9h
P R E L I M I N A R Y
Group Priority
X
4
(Table
[2:1]
W
43) defines which interrupts hold the highest
X
3
Group B
Priority
W
X
2
Group C
Priority
W
X
1
Product Specification
ZLP12840 OTP MCU
Group Priority
[0]
W
X
0
Interrupts
89

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