ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 55

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

PS024410-0108
Receiving Data Using the Polled Method
Receiving Data Using the Interrupt-Driven Method
Follow the steps below to configure the UART for polled data reception:
1. Write to the BCNST register to set the appropriate baud rate.
2. Write to the UART control register (UCTL) to:
3. Check the receive status bit in the UART Status register, bit UST[7], to determine if
4. Read data from the UART Receive Data register.
5. Return to
The UART Receiver interrupt indicates the availability of new data (as well as error
conditions). Follow the steps below to configure the UART receiver for interrupt-driven
operation:
1. Write to the UART BRG Constant registers to set the appropriate baud rate.
2. Execute a DI instruction to disable interrupts.
3. Write to the interrupt control registers to enable the UART receiver interrupt and set
4. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
5. Write to the UART Control register (UCTL) to:
6. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Checks the UART Status register to determine the source of the interrupt, whether it is
2. Reads the data from the UART Receive Data register if the interrupt was caused by
(a) Set the receive enable bit (UCTL[6]) to enable the UART for data reception
(b) Enable parity, if appropriate and select either even or odd parity
the Receive Data register contains a valid data byte (indicated by a 1). If UST[7] is set
to 1 to indicate available data, continue to
(indicated by a 0), continue to monitor the UST[7] bit awaiting reception of the valid
data.
the appropriate priority.
(a) Set the receive enable bit (UCTL[6]) to enable the UART for data reception.
(b) Enable parity, if appropriate, and select either even or odd parity.
an error, break, or received data.
data available.
step 3
to receive additional data.
P R E L I M I N A R Y
step
4. If the Receive Data register is empty
Universal Asynchronous Receiver/
Product Specification
ZLP12840 OTP MCU
49