ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 108

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

[
Table 48. Stop Mode Recovery Register (SMR)
PS024410-0108
Bit
Field
Reset
R/W
Address
Bit
Position
[7]
[6]
[5]
[4:2]
[1]
[0]
Value Description
000
001
010
100
101
011
110
111
Stop
Flag
—
0
1
0
1
0
1
0
1
R
7
0
Stop Flag—Indicates whether last startup was power-on Reset or Stop Mode
Recovery. A write to this bit has no effect.
Power-On Reset.
Stop Mode Recovery.
Stop Mode Recovery Level—Selects whether an SMR[4:2]-selected SMR is initiated
by a Low or High level at the XOR-gate input (see
Low.
High.
Stop Delay—Controls the reset delay after recovery. Must be 1 if using a crystal or
resonator clock source.
Off.
On.
Stop Mode Recovery Source—Specifies a Stop Mode Recovery wake-up source at the
XOR gate input (see
Mode Recovery. The following equations ignore any Port pin configured as output or
selected in SMR1 or SMR3.
No SMR register source selected.
Reserved.
P31.
P32.
P33.
P27.
Port 2 NOR 0–3.
Port 2 NOR 0–7.
Reserved—Reads are undefined; must write 0.
SCLK/TCLK Divide-by-16 Select—Controls a divide-by-16 prescaler of the internal
SCLK/TCLK signal (see
Power-On Reset or Stop Mode Recovery clears this bit to 0.
OFF.
ON.
Recovery Level
Stop Mode
W
6
0
Figure 35
P R E L I M I N A R Y
Delay
Stop
W
Internal Clock Signals (SCLK and TCLK)
5
1
Bank F: 0Bh; Linear: F0Bh
on page 101). This value is not changed by a Stop
Stop Mode Recovery
W
4
0
Source
W
3
0
W
2
0
Figure 35
Reserved
Resets and Power Management
on page 101).
Product Specification
W
1
0
ZLP12840 OTP MCU
on page 94). A
Divide-by-16
SCLK/TCLK
W
0
0
102