ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 38

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

PS024410-0108
Linear Memory Addressing
But if:
R253 RP = 0Dh
R0 = CTR0
R1 = CTR1
R2 = CTR2
R3 = CTR3
The counter/timers are mapped into ERF group D. Access is easily performed using the
following code segment.
LD RP, #0Dh
LD R0,#xx
LD 1, #xx
LD R1, 2
LD RP, #7Dh
LD 71h, 2
LD R1, 2
In addition to using the RP Register to designate a bank and working register group for 8-
bit or 4-bit addressing, programs can use 12-bit linear addressing to load a register in any
other bark to or from a register in the current bank. Linear addressing is implemented in
the LDX and LDXI instructions only. Linear addressing treats the register file as if all of
the registers are logically ordered end-to-end, as opposed to being grouped into banks and
working register groups, as displayed in
register file addresses are numbered sequentially from Bank 0, register 00h to Bank 0,
register FFh, then continuing with Bank 1, register 00h, and so on up to Bank F, register
FFh.
Using the LDX and/or the LDXI instructions, either the target or destination register
location can be addressed through a 12-bit linear address value stored in a general-purpose
register pair. For example, the following code uses linear addressing for the source of a
register transfer operation and uses a working register address for the target.
SRP #%23
LD R0, #%55
SRP #%12
LD R6, #%03
LD R7, #%20
LD R0, @RR6
; Select ERF D for access to Bank D
; (working register group 0)
; load CTR0
; load CTR1
; CTR2 → CTR1
; Select Expanded Register Bank D and working
; register group 7 of Bank 0 for access.
; CTR2 → register 71h
; CTR2 → register 71h
;Set working register group 2 in bank 3
;Load 55 into working register R0 in the current
;group and bank (linear address 320h)
;Set working register group 1 in bank 2
;Load high byte of source linear address (0320h)
;Load low byte of source linear address (0320h)
;Load linear address 320h contents (55h) into
;working register R0 in the current group and
;bank (linear address 210h)
P R E L I M I N A R Y
Figure 11
on page 33. For linear addressing,
Product Specification
ZLP12840 OTP MCU
Memory and Registers
32