ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 105

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

PS024410-0108
STOP Mode
Note:
Fast Stop Mode Recovery
Stop Mode Recovery Interrupt
Power consumption during HALT mode can be reduced by first setting SMR[0]=1 to
enable the divide-by-16 clock prescaler.
This instruction turns OFF the internal clock and external crystal oscillation, reducing the
MCU supply current to a very low level. For STOP mode current specifications, see
Characteristics
To enter STOP mode, first flush the instruction pipeline to avoid suspending execution in
mid-instruction. Execute a NOP (Op Code =
sleep instruction, as follows:
STOP mode is terminated only by a reset, such as WDT time-out, POR, or one of the SMR
events described in the following sections. This condition causes the processor to restart
the application program at address
Unlike a normal POR or WDT reset, a SMR reset does not reset the contents of some reg-
isters and bits. Register bits not reset by a SMR are highlighted in grey in the register
tables. Register bit SMR[7] is set to 1 by a SMR.
SMR[5] can be cleared to 0 before entering STOP mode to bypass the default T
timer upon SMR. See
must be kept active for at least 10 input clock periods (TpC).
SMR[5] must be set to 1 if using a crystal or resonator clock source. The T
allows the clock source to stabilize before executing instructions.
Software can set register bit SMR4[4] = 1 to enable routing of SMR events to IRQ1 and to
Port 3, pin 3. In this configuration, if an IRQ1 interrupt occurs, register bit P3[3] = 0 indi-
cates that a SMR event is occurring.
FF
7F
FF
6F
on page 129.
NOP
HALT
NOP
STOP
Power-On Reset Timer
P R E L I M I N A R Y
000Ch
; clear the pipeline
; enter HALT mode
; clear the pipeline
; enter STOP mode
.
FFh
on page 97. If SMR[5]=0, the SMR source
) immediately before the appropriate
Resets and Power Management
Product Specification
ZLP12840 OTP MCU
POR
delay
POR
reset
DC
99