ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 57

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

PS024410-0108
Note:
•
It is important to ensure that the transmitter uses the same stop bit configuration as the
receiver.
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status (UST) register is updated to indicate
the overrun condition (and Break Detect, if applicable). The UST[7] bit is set to 1 to indi-
cate that the Receive Data register contains a data byte. However, because the overrun
error occurred, this byte may not contain valid data and should be ignored. The Break
Detect bit, UST[3], indicates if the overrun was caused by a break condition on the line.
After reading the status byte indicating an overrun error, the Receive Data register must be
read again to clear the error bits is the UART Status 0 register. Updates to the Receive
Data register occur only when the next data word is received.
UART Data and Error Handling Procedure
Figure 16
interrupt service routines.
will be generated when the UART Receive Data register is read. The interrupt is
cleared by reading the UART Receive Data register. When an overrun error occurs,
the additional data byte will not overwrite the data currently stored in the UART
Receive Data register.
A data framing error is detected—A data framing error is detected when the first stop
bit is 0 instead of 1. When configured for 2 stop bits, a data framing error is only
detected when the first stop bit is 0. A framing error interrupt is generated when the
framing error is detected. Reading the UART Receive Data register clears the
interrupt.
on page 52 displays the recommended procedure for use in UART receiver
P R E L I M I N A R Y
Universal Asynchronous Receiver/
Product Specification
ZLP12840 OTP MCU
51