ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 118

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

Table 53. Watchdog Timer Mode Register (WDTMR)
PS024410-0108
Bit
Field
Reset
R/W
Address
Bit
Position Value Description
[7:4]
[3]
[2]
Watchdog Timer
Note:
—
0
1
0
1
X
X
7
The Watchdog Timer is a retriggerable one-shot timer that resets the Z8 LXM CPU if it
reaches its terminal count. The WDT must initially be enabled by executing the WDT
instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The
WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero
(Z), Sign (S), and Overflow (V) Flags.
The POR clock source is the internal RC-oscillator. Bits 0 and 1 of the WDT register con-
trol a tap circuit that determines the minimum time-out period. Bit 2 determines whether
the WDT is active during HALT, and bit 3 determines WDT activity during STOP mode.
Bits 4 through 7 are reserved (see
first 60 processor cycles (120 XTAL clocks) from the execution of the first instruction
after Power-On Reset, Watchdog Timer Reset, or a SMR (see
After this point, the register cannot be modified by any means (intentional or otherwise).
The WDTMR register cannot be read. The register is located in Bank F of the Expanded
Register Group at address location 0Fh.
This register is not reset after a SMR.
Reserved—Reads are undefined; must write 0000.
WDT During STOP Mode—
STOP mode.
Off.
WDT active during STOP mode.
WDT During HALT Mode—
HALT mode. See
Off.
WDT active during HALT mode.
X
X
6
—
X
X
5
X
X
4
Figure 34
P R E L I M I N A R Y
WDT During STOP
Bank F: 0Fh; Linear: F0Fh
Determines whether the WDT is active or not during
Determines whether or not the WDT is active during
on page 96
Table
Mode
W
3
1
53). This register is accessible only during the
.
WDT During HALT
Mode
W
2
1
Resets and Power Management
STOP Mode
Product Specification
ZLP12840 OTP MCU
Time-Out Select
W
1
0
on page 99).
W
0
1
112