ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 85
ZLP128ICE01ZEM
Manufacturer Part Number
ZLP128ICE01ZEM
Description
EMULATOR CRIMZON Z8 ZLP12840
Manufacturer
Zilog
Datasheets
1.ZLP128ICE01ZEM.pdf
(5 pages)
2.ZLP128ICE01ZEM.pdf
(157 pages)
3.ZLP128ICE01ZEM.pdf
(70 pages)
Specifications of ZLP128ICE01ZEM
Interface Type
RS-232, Ethernet, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3829
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Table 37. Timer 8 and Timer 16 Common Functions Register (CTR1)
PS024410-0108
Bit
Field
Reset
R/W
Address
Bit
Position
[7]
[6]
[5:4]
Mode
R/W
Mode—Selects the timer mode for signal transmission or demodulation.
TRANSMIT Mode
P36 Out—Select normal I/O or timer output on Port 3, Pin 6.
DEMODULATION Mode
Demodulator Input—Select Port 2, Pin 0 or Port 3, Pin 1 as the counter/timer input.
TRANSMIT Mode
T8/T16 Logic—Defines how the Timer 8/Timer 16 outputs are combined logically.
These bits are not reset upon Stop Mode Recovery.
DEMODULATION Mode
Edge Detect—Define the behavior of the edge detector.
Description
7
0
00
01
10
00
01
10
11
11
0
1
0
1
0
1
TRANSMIT mode.
DEMODULATION mode.
P36 acts as normal I/O port output.
P36 acts as combined Timer 8/Timer 16 output.
P31 acts as the demodulator input. If IMR[2] = 1, a P31 event can also generate
an IRQ1 interrupt. To prevent this, clear IMR[2] or select P20 as input instead.
P20 acts as the demodulator input.
Output is T8 AND T16.
Output is T8 OR T16.
Output is T8 NOR T16.
Output is T8 NAND T16.
Falling edge detection.
Rising edge detection.
Falling and rising edge detection.
Reserved.
Demodulator
P36 Out/
Input
R/W
6
0
T8/T16 Logic/
Edge Detect
R/W
5
0
P R E L I M I N A R Y
R/W
Bank D: 01h; Linear: D01h
4
0
R/W
Glitch Filter
3
0
Submode/
Transmit
R/W
2
0
Initial Timer 8
Rising Edge
R/W
Out/
1
0
Product Specification
Initial Timer 16
Falling Edge
Out/
R/W
0
0
Timers
79
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