ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 54

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

PS024410-0108
Caution:
Caution:
Transmitting Data Using the Interrupt-Driven Method
6. To transmit additional bytes, return to
7. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If
The UART transmitter interrupt indicates the availability of the Transmit Data register to
accept new data for transmission. Follow the steps below to configure the UART for
interrupt-driven data transmission:
1. Write to the BCNST register to set the appropriate baud rate.
2. Write a 0 to bit 6 of the P01M register.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and
5. Write to the UART Control register to:
6. Execute an EI instruction to enable interrupts.
7. Because the transmit buffer is empty, an interrupt is immediately executed.
8. Write the data byte to the UART Transmit Data register. The transmitter automatically
9. Execute the IRET instruction to return from the interrupt-service routine and wait for
10. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If
Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted.
Data written while the transmit data status bit is clear (UST[2]=0) overwrites the
previous value written, so the previous written value will not be transmitted. Disabling
the UART transmitter while the transmit completion status bit is clear (UST[1]=0) can
corrupt the byte being transmitted.
Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted.
Data written while the transmit data status bit is clear (UST[2]=0) overwrites the
previous value written, so the previous written value will not be transmitted. Disabling
the UART transmitter while the transmit completion status bit is clear (UST[1]=0) can
corrupt the byte being transmitted.
UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all
data in the Transmit Data and internal shift registers has been transmitted.
set the appropriate priority.
(a) Set the transmit enable bit (UCTL bit 7) to enable the UART for data transmission.
(b) Enable parity, if appropriate, and select either even or odd parity.
transfers the data to the internal transmit shift register and transmits the data.
the Transmit Data register to again become empty.
UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all
data in the Transmit Data and internal shift registers has been transmitted.
P R E L I M I N A R Y
step
4.
Universal Asynchronous Receiver/
Product Specification
ZLP12840 OTP MCU
48