ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 104
ZLP128ICE01ZEM
Manufacturer Part Number
ZLP128ICE01ZEM
Description
EMULATOR CRIMZON Z8 ZLP12840
Manufacturer
Zilog
Datasheets
1.ZLP128ICE01ZEM.pdf
(5 pages)
2.ZLP128ICE01ZEM.pdf
(157 pages)
3.ZLP128ICE01ZEM.pdf
(70 pages)
Specifications of ZLP128ICE01ZEM
Interface Type
RS-232, Ethernet, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3829
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Table 47. Low-Voltage Detection Register (LVD)
PS024410-0108
Bit
Field
Reset
R/W
Address
Bit
Position R/W Value Description
[7:3]
[2]
[1]
[0]
HALT Mode
Note:
R/W
—
R
R
real time. The HVD Flag (bit 2 of the LVD register) is set only if V
V
When Voltage Detection is enabled, the LVD Flag also triggers IRQ5. The IRQ bit 5
latches the low voltage condition until it is cleared by instructions or reset. The IRQ5
interrupt is served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is
latched as a Flag only.
Do not modify register P01M while checking a low-voltage condition. Switching noise
coming from Port 0 can trigger the LVD Flag.
Voltage detection does not work in STOP mode. This register is described in
This instruction turns off the internal CPU clock, but not the XTAL oscillation. The
counter/timers, UART, and interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain
active. The devices are recovered by interrupts, either externally or internally generated.
An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt
service routine, the program continues from the instruction after HALT mode.
To enter HALT mode, first flush the instruction pipeline to avoid suspending execution in
mid-instruction. Execute a NOP (Op Code =
sleep instruction, as follows:
R
7
1
HVD.
—
0
1
0
1
0
1
The LVD Flag (bit 1 of the LVD register) is set only if V
HVD clear.
High voltage detected. V
LVD clear.
Low voltage detected. V
Voltage detection disabled.
Voltage detection enabled.
Reserved—Reads 11111b. Writes have no effect.
R
6
1
Reserved
R
5
1
P R E L I M I N A R Y
Bank D: 0Ch; Linear: D0Ch
R
4
1
CC
CC
>V
>V
LVD
HVD
R
3
1
FFh
High Battery
) immediately before the appropriate
Detect
R
2
0
Resets and Power Management
Low Battery
CC
Product Specification
Detect
ZLP12840 OTP MCU
is lower than the V
CC
R
1
0
is higher than
Detect Enable
Table
Voltage
R/W
0
0
47.
LVD
.
98
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