EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 87

• Manufacturer Part Number: EVAL-ADUC7023QSPZ
• Description: KIT DEV FOR ADUC7023 QUICK START
• Manufacturer: Analog Devices Inc
• Type: MCUr

Specifications of EVAL-ADUC7023QSPZ

• Contents: Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• For Use With/related Products: ARM7TDMI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7023 operational power supply voltage range is 2.7 V
to 3.6 V. Separate analog and digital power supply pins (AV
and IOV
noisy digital signals often present on the system IOV
this mode, the part can also operate with split supplies, that is, it
can use different voltage levels for each supply. For example, the
system can be designed to operate with an IOV
of 3.3 V while the AV
typical split supply configuration is shown in Figure 46.
As an alternative to providing two separate power supplies, the
user can reduce noise on AV
and/or ferrite bead between AV
AV
shown in Figure 47. With this configuration, other analog circuitry
(such as op amps, voltage reference, and others) can be powered
from the AV
In both Figure 46 and Figure 47, a large value (10 μF) reservoir
capacitor sits on IOV
AV
located at each AV
design practice, include all of these capacitors and ensure the
smaller capacitors are close to each AV
as short as possible. Connect the ground terminal of each of
these capacitors directly to the underlying ground plane.
Finally, the analog and digital ground pins on the ADuC7023
must be referenced to the same system ground reference point
at all times.
IOV
The IOV
is the supply source for the internal oscillator and PLL circuits.
DIGITAL SUPPLY
DIGITAL SUPPLY
DD
DD
DD
. In addition, local small-value (0.1 μF) capacitors are
0.1µF
separately to ground. An example of this configuration is
Supply Sensitivity
10µF
0.1µF
DD
DD
, respectively) allow AV
supply is sensitive to high frequency noise because it
DD
10µF
Figure 47. External Single Supply Connections
Figure 46. External Dual Supply Connections
0.1µF
supply line as well.
0.1µF
DD
DD
and IOV
DD
IOV
IOGND
, and a separate 10 μF capacitor sits on
IOV
IOGND
level can be at 3 V, or vice versa. A
ADuC7023
DD
ADuC7023
DD
BEAD
DD
DD
DD
by placing a small series resistor
REFGND
GND
pin of the chip. As per standard
and IOV
GND
AGND
DD
AGND
AV
AV
REF
REF
DD
to be kept relatively free of
DD
DD
DD
1.6V
pin with trace lengths
, and then decoupling
10µF
ANALOG SUPPLY
DD
10µF
voltage level
0.1µF
0.1µF
DD
line. In
0.1µF
DD
Rev. B | Page 87 of 96
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature is
to ensure that no flash interface timings or ARM7TDMI
timings are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise soures below
50 mV on IOV
recommended.
Linear Voltage Regulator
Each ADuC7023 requires a single 3.3 V supply, but the core
logic requires a 2.6 V supply. An on-chip linear regulator
generates the 2.6 V from IOV
is the 2.6 V supply for the core logic. An external compensation
capacitor of 0.47 μ F must be connected between LV
DGND (as close as possible to these pins) to act as a tank of
charge, as shown in Figure 49.
The LV
recommended to use excellent power supply decoupling on
IOV
on-chip voltage regulator.
DD
to help improve line regulation performance of the
DD
DIGITAL
SUPPLY
pin should not be used for any other chip. It is also
Figure 48. Recommended IOV
Figure 49. Voltage Regulator Connections
DD
, a filter such as the one shown in Figure 48 is
0.47µF
1µH
0.1µF
10µF
LV
DGND
0.1µF
DD
DD
ADuC7023
for the core logic. The LV
DD
IOV
IOGND
Supply Filter
ADuC7023
DD
ADuC7023
DD
and
DD
pin