EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 81

• Manufacturer Part Number: EVAL-ADUC7023QSPZ
• Description: KIT DEV FOR ADUC7023 QUICK START
• Manufacturer: Analog Devices Inc
• Type: MCUr

Specifications of EVAL-ADUC7023QSPZ

• Contents: Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• For Use With/related Products: ARM7TDMI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF
changes the register to 0x08 and writing 0xFF a second time
changes the register to 0x00.
Name:
Address:
Default value:
Access:
Table 97. FIQSTAN MMR Bit Designations
Bit
31 to 8
7 to 0
External Interrupts and PLA interrupts
The ADuC7023 provides up to four external interrupt sources
and two PLA interrupt sources. These external interrupts can be
individually configured as level or rising/falling edge triggered.
To enable the external interrupt source or the PLA interrupt
source, the appropriate bit must be set in the FIQEN or IRQEN
register. To select the required edge or level to trigger on, the
IRQCONE register must be appropriately configured.
To properly clear an edge-based external IRQ interrupt or an
edge-based PLA interrupt, set the appropriate bit in the
IRQCLRE register.
IRQCONE Register
Name:
Address:
Default value:
Access:
Table 98. IRQCONE MMR Bit Designations
Bit
31 to 12
11 to 10
Name
Reserved
Value
11
10
01
00
FIQSTAN
0xFFFF013C
0x00000000
Read/write
IRQCONE
0xFFFF0034
0x00000000
Read and write
Name
Reserved
PLA1SRC[1:0]
Description
These bits are reserved and should not be
written to.
This bit is set to 1 to enables nesting of
FIQ interrupts.
When this bit is cleared, it means no
nesting or prioritization of FIQs is
allowed.
Description
These bits are reserved and
should not be written to.
PLA IRQ1 triggers on falling
edge.
PLA IRQ1 triggers on rising
edge.
PLA IRQ1 triggers on low
level.
PLA IRQ1 triggers on high
level.
Rev. B | Page 81 of 96
Bit
9 to 8
7 to 6
5 to 4
3 to 2
1 to 0
IRQCLRE Register
Name:
Address:
Default value:
Access:
Value
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
IRQCLRE
0xFFFF0038
0x00000000
Read and write
Name
IRQ3SRC[1:0]
IRQ2SRC[1:0]
PLA0SRC[1:0]
IRQ1SRC[1:0]
IRQ0SRC[1:0]
Description
External IRQ3 triggers on
falling edge.
External IRQ3 triggers on
rising edge.
External IRQ3 triggers on
low level.
External IRQ3 triggers on
high level.
External IRQ2 triggers on
falling edge.
External IRQ2 triggers on
rising edge.
External IRQ2 triggers on
low level.
External IRQ2 triggers on
high level.
PLA IRQ0 triggers on falling
edge.
PLA IRQ0 triggers on rising
edge.
PLA IRQ0 triggers on low
level.
PLA IRQ0 triggers on high
level.
External IRQ1 triggers on
falling edge.
External IRQ1 triggers on
rising edge.
External IRQ1 triggers on
low level.
External IRQ1 triggers on
high level.
External IRQ0 triggers on
falling edge.
External IRQ0 triggers on
rising edge.
External IRQ0 triggers on
low level.
External IRQ0 triggers on
high level.
ADuC7023