EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 38

• Manufacturer Part Number: EVAL-ADUC7023QSPZ
• Description: KIT DEV FOR ADUC7023 QUICK START
• Manufacturer: Analog Devices Inc
• Type: MCUr

Specifications of EVAL-ADUC7023QSPZ

• Contents: Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• For Use With/related Products: ARM7TDMI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
FEEMOD Register
Name:
Address:
Default value:
Access:
Function:
Table 31. FEEMOD MMR Bit Designations
Bit
15 to 9
8
7 to 5
4
3
2 to 0
FEECON Register
Name:
Address:
Default value:
Access:
Function:
Table 32. Command Codes in FEECON
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
1
1
1
1
1
1
1
Command
Null
Single read
Single write
Erase/write
Single verify
Single erase
Mass erase
Reserved
Reserved
Reserved
Reserved
Signature
Protect
Description
Reserved.
Reserved. Always set this bit to 0.
Reserved. Always set this bit to 0 except when writing keys. See the Sequence to Write the Key section.
Flash/EE interrupt enable.
This bit is set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.
This bit is cleared by the user to disable the Flash/EE interrupt.
Erase/write command protection.
This bit is set by the user to enable the erase and write commands.
This bit is cleared to protect the Flash/EE against erase/write command.
Reserved. Always set this bit to 0.
FEEMOD
0xFFFFF804
0x0000
Read/write
FEEMOD sets the operating mode of the flash control interface. Table 31 shows FEEMOD MMR bit designations.
FEECON
0xFFFFF808
0x07
Read/write
FEECON is an 8-bit command register. The commands are described in Table 32.
Description
Idle state.
Load FEEDAT with the 16-bit data. Indexed by FEEADR.
Write FEEDAT at the address pointed by FEEADR. This operation takes 50 μs.
Erase the page indexed by FEEADR, and write FEEDAT at the location pointed by FEEADR. This operation takes
approximately 24 ms.
Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The result of the comparison is
returned in FEESTA Bit 1.
Erase the page indexed by FEEADR.
Erase 62 kB of user space. The 2 kB of kernel are protected. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction. See the Command Sequence for
Executing a Mass Erase section.
Reserved.
Reserved.
Reserved.
Reserved.
Give a signature of the 64 kB of Flash/EE in the 24-bit FEESIGN MMR. This operation takes 32,778 clock cycles.
This command can run one time only. The value of FEEPRO is saved and removed only with a mass erase (0x06) or
the key (FEEADR/FEEDAT).
Rev. B | Page 38 of 96