EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
EVAL-ADUC7023QSPZ
Manufacturer Part Number
EVAL-ADUC7023QSPZ
Description
KIT DEV FOR ADUC7023 QUICK START
Manufacturer
Analog Devices Inc
Type
MCUr
Datasheet
1.EVAL-ADUC7023QSPZ.pdf
(96 pages)
Specifications of EVAL-ADUC7023QSPZ
Contents
Board
Silicon Manufacturer
Analog Devices
Core Architecture
ARM
Core Sub-architecture
ARM7TDMI
Silicon Core Number
ADuC7023
For Use With/related Products
ARM7TDMI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Address
0x0530
0x0534
0x0544
0x0548
Table 16. DAC Address Base = 0xFFFF0600
Address
0x0600
0x0604
0x0608
0x060C
0x0610
0x0614
0x0618
0x061C
0x0654
0x0650
0x0658
Table 17. I
Address
0x0800
0x0804
0x0808
0x080C
0x0810
0x0814
0x0818
0x081C
0x0824
0x0828
0x082C
0x0830
0x0834
0x0838
0x083C
0x0840
0x0844
0x0848
0x084C
Table 18. I
Address
0x0900
0x0904
0x0908
0x090C
0x0910
2
2
Name
I2C0MCON
I2C0MSTA
I2C0MRX
I2C0MTX
I2C0MCNT0
I2C0MCNT1
I2C0ADR0
I2C0ADR1
I2C0DIV
I2C0SCON
I2C0SSTA
I2C0SRX
I2C0STX
I2C0ALT
I2C0ID0
I2C0ID1
I2C0ID2
I2C0ID3
I2C0FSTA
Name
I2C1MCON
I2C1MSTA
I2C1MRX
I2C1MTX
I2C1MCNT0
C0 Base Address = 0XFFFF0800
C1 Base Address = 0XFFFF0900
Name
ADCGN
ADCOF
TSCON
TEMPREF
Name
DAC0CON
DAC0DAT
DAC1CON
DAC1DAT
DAC2CON
DAC2DAT
DAC3CON
DAC3DAT
DACBCFG
DACBKEY0
DACBKEY1
Byte
2
2
1
1
2
1
1
1
2
2
2
1
1
1
1
1
1
1
2
Byte
2
2
1
1
2
Byte
2
2
1
2
Access
Type
R/W
R
R
W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
Access Type
R/W
R
R
W
R/W
Access Type
R/W
R/W
R/W
R/W
Byte
1
4
1
4
1
4
1
4
1
2
2
Default
Value
0x0000
0x0000
0x00
0x00
0x0000
0x00
0x00
0x00
0x1F1F
0x0000
0x0000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0000
0x0000
0x0000
0x00
0x00
0x0000
Default Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
Access Type
Default Value
Factory configured
Factory configured
0x00
Factory configured
Description
I
I
I
I
I
register prior to reading from a slave device.
I
bytes already received during a read from slave sequence.
I
communications.
I
communications. Used in 10-bit mode only.
I
I
I
I
I
I
I
I
I
I
I
Rev. B | Page 25 of 96
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C0 master control register.
C0 master status register.
C0 master receive register.
C0 master transmit register.
C0 master read count register. Write the number of required bytes into this
C0 master current read count register. This register contains the number of
C0 address byte register. Write the required slave address in here prior to
C0 address byte register. Write the required slave address in here prior to
C0 clock control register. Used to configure the SCLK frequency.
C0 slave control register.
C0 slave status register.
C0 slave receive register.
C0 slave transmit register.
C0 hardware general call recognition register.
C0 slave ID0 register. Slave bus ID register.
C0 slave ID1 register. Slave bus ID register.
C0 slave ID2 register. Slave bus ID register.
C0 slave ID3 register. Slave bus ID register.
C0 FIFO status register. Used in both master and slave modes.
Description
I
I
I
I
I
into this register prior to reading from a slave device.
2
2
2
2
2
C1 master control register.
C1 master status register.
C1 master receive register.
C1 master transmit register.
C1 master read count register. Write the number of required bytes
Default Value
0x00
0x00000000
0x00
0x00000000
0x00
0x00000000
0x00
0x00000000
0x00
0x0000
0x0000
Description
ADC gain calibration MMR.
ADC offset calibration MMR.
Temperature sensor chopping enable register.
Temperature sensor reference value.
Description
DAC0 control MMR.
DAC0 data MMR.
DAC1 control MMR.
DAC1 data MMR.
DAC2 control MMR.
DAC2 data MMR.
DAC3 control MMR.
DAC3 data MMR.
DAC Configuration MMR
DAC Key0 MMR
DAC Key1 MMR
ADuC7023