EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 54

• Manufacturer Part Number: EVAL-ADUC7023QSPZ
• Description: KIT DEV FOR ADUC7023 QUICK START
• Manufacturer: Analog Devices Inc
• Type: MCUr

Specifications of EVAL-ADUC7023QSPZ

• Contents: Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• For Use With/related Products: ARM7TDMI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
Table 62. SPISTA MMR Bit Designations
Bit
15 to 12
11
10 to 8
7
6
5
4
3 to 1
0
SPIRX Register
Name:
Address:
Default value:
Access:
Function:
Name
SPIREX
SPIRXFSTA[2:0]
SPIFOF
SPIRXIRQ
SPITXIRQ
SPITXUF
SPITXFSTA[2:0]
SPIISTA
SPIRX
0xFFFF0A04
0x00
Read
This 8-bit MMR is the SPI receive register.
Description
Reserved bits.
SPI Rx FIFO excess bytes present.
This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON
This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE.
SPI Rx FIFO status bits.
[000] = Rx FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
SPI Rx FIFO overflow status bit.
This bit is set when the Rx FIFO is full when new data is loaded to the FIFO. This bit generates an interrupt
except when SPIRFLH is set in SPICON.
This bit is cleared when the SPISTA register is read.
SPI Rx IRQ status bit.
This bit is set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the
required number of bytes have been received.
This bit is cleared when the SPISTA register is read.
SPI Tx IRQ status bit.
This bit is set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required
number of bytes have been transmitted.
This bit is cleared when the SPISTA register is read.
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt
except when SPITFLH is set in SPICON.
This bit is cleared when the SPISTA register is read.
SPI Tx FIFO status bits.
[000] = Tx FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
SPI interrupt status bit.
This bit is set to 1 when an SPI based interrupt occurs.
This bit is cleared after reading SPISTA.
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SPITX Register
Name:
Address:
Default value:
Access:
Function:
SPITX
0xFFFF0A08
0xXX
Write
This 8-bit MMR is the SPI transmit register.