EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 47

• Manufacturer Part Number: EVAL-ADUC7023QSPZ
• Description: KIT DEV FOR ADUC7023 QUICK START
• Manufacturer: Analog Devices Inc
• Type: MCUr

Specifications of EVAL-ADUC7023QSPZ

• Contents: Board
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• For Use With/related Products: ARM7TDMI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OSCILLATOR AND PLL—POWER CONTROL
Clocking System
Each ADuC7023 integrates a 32.768 kHz ± 3% oscillator, a clock
divider, and a PLL. The PLL locks onto a multiple (1275) of the
internal oscillator or an external 32.768 kHz crystal to provide a
stable 41.78 MHz clock (UCLK) for the system. To allow power
saving, the core can operate at this frequency, or at binary
submultiples of it. The actual core operating frequency, UCLK/2
is referred to as HCLK. The default core clock is the PLL clock
divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency
can also come from an external clock on the ECLK pin as
described in Figure 36.
Table 46. Operating Modes
Mode
Active
Pause
Nap
Sleep
Stop
X = don’t care.
Table 47. Typical Current Consumption at 25°C in mA
PC[2:0]
000
001
010
011
100
WATCHDOG
*32.768kHz ±3%
TIMERS
TIMER
CORE
Core
Yes
Mode
Active
Pause
Nap
Sleep
Stop
OSCILLATOR
INTERNAL
OCLK 32.768kHz
Figure 36. Clocking System
32kHz*
Peripherals
X
X
PLL
I
2
C
CD
CD = 0
28
14
5
0.23
0.23
41.78MHz
UCLK
AT POWER UP
OSCILLATOR
P1.2/ECLK
CRYSTAL
/2
CD
HCLK
PERIPHERALS
MDCLK
CD = 1
17
ANALOG
9
4.5
0.23
0.23
PLL
X
X
X
XTAL/T2/T3
X
X
X
X
XCLKO
XCLKI
P1.2/XCLK
CD = 2
12
7.6
4.5
0.23
0.23
Rev. B | Page 47 of 96
CD
,
CD = 3
11
5.7
4.5
0.23
0.23
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
In noisy environments, noise can couple to the external crystal
pins, and PLL may quickly lose lock. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is only serviced when the lock is restored.
In case of crystal loss, use the watchdog timer. During
initialization, a test on the RSTSTA can determine if the reset
came from the watchdog timer.
Power Control System
A choice of operating modes is available on the ADuC7023.
Table 46 describes what part is powered on in the different
modes and indicates the power-up time.
Table 47 gives some typical values of the total current consumption
(analog + digital supply currents) in the different modes,
depending on the clock divider bits. The ADC is turned off.
Note that these values also include current consumption of the
regulator and other parts on the test board where these values
are measured.
IRQ0 to IRQ3
X
X
X
X
X
CD = 4
9.3
4.8
4.5
0.23
0.23
Start-Up/Power-On Time
66 ms at CD = 0
230 ns at CD = 0; 3 μs at CD = 7
283 ns at CD = 0; 3 μs at CD = 7
1.23 ms
1.45 ms
CD = 5
7.5
4.6
4.5
0.23
0.23
CD = 6
7.2
4.6
4.5
0.23
0.23
ADuC7023
CD = 7
7
4.6
4.5
0.23
0.23