M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 217

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SRW — Slave Read/Write
IICIF — IIC Interrupt Flag
RXAK — Receive Acknowledge
13.5.5
DATA — Data
Freescale Semiconductor
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When addressed as a slave the SRW bit indicates the value of the R/W command bit of the calling
address sent to the master.
The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by writing a
one to it in the interrupt routine. One of the following events can set the IICIF bit:
When the RXAK bit is low, it indicates an acknowledge signal has been received after the completion
of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next
byte of data.
In slave mode, the same functions are available after an address match has occurred.
1 = Slave transmit, master reading from slave.
0 = Slave receive, master writing to slave.
One byte transfer completes
Match of slave address to calling address
Arbitration lost
1 = Interrupt pending.
0 = No interrupt pending.
1 = No acknowledge received.
0 = Acknowledge received.
IIC Data I/O Register (IIC1D)
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IIC1D register to prevent an inadvertent
initiation of a master receive data transfer.
Reset:
Read:
Write:
Bit 7
0
Figure 13-9. IIC Data I/O Register (IIC1D)
MC9S08GB/GT Data Sheet, Rev. 2.3
6
0
5
0
NOTE
4
0
DATA
3
0
2
0
Inter-Integrated Circuit (IIC) Module
1
0
Bit 0
0
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