M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 106

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Internal Clock Generator (ICG) Module
The ICG will remain in this state while the count error (∆n) is greater than the maximum n
the minimum n
In this state the output clock signal ICGOUT frequency is given by f
7.3.3.2
FLL engaged internal locked is entered from FEI unlocked when the count error (∆n), which comes from
the subtractor, is less than n
required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is
given by f
The update made is an average of the error measurements taken in the four previous comparisons.
7.3.4
FLL bypassed external (FBE) is entered when any of the following conditions occur:
In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock,
ICGERCLK. The output clock signal ICGOUT frequency is given by f
source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range
0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for
RANGE = 0 or high for RANGE = 1.
7.3.5
The FLL engaged external (FEE) mode is entered when any of the following conditions occur:
In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL
loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To
run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The
maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO.
The minimum multiplier for the FLL, from
operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.
7.3.5.1
FEE unlocked is entered when FEE is entered and the count error (∆n) output from the subtractor is greater
than the maximum n
unlock condition.
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From SCM when CLKS = 10 and ERCS is high
When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited
From FLL engaged external mode if a loss of DCO clock occurs and the external reference is still
valid (both LOCS = 1 and ERCS = 1)
CLKS = 11 and ERCS and DCOS are both high.
The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.
ICGDCLK
FLL Bypassed, External Clock (FBE) Mode
FLL Engaged, External Clock (FEE) Mode
FLL Engaged Internal Locked
FLL Engaged External Unlocked
lock
, as required by the lock detector to detect the lock condition.
/ R. In FEI locked, the filter value is only updated once every four comparison cycles.
unlock
or less than the minimum n
lock
(max) and greater than n
MC9S08GB/GT Data Sheet, Rev. 2.3
Table 7-7
unlock
is 4. Because 4 X 10 MHz is 40MHz, which is the
lock
, as required by the lock detector to detect the
(min) for a given number of samples, as
ICGDCLK
ICGERCLK
/ R.
/ R. If an external clock
Freescale Semiconductor
lock
or less than