C8051F336DK Silicon Laboratories Inc, C8051F336DK Datasheet - Page 138

• Manufacturer Part Number: C8051F336DK
• Description: DEV KIT FOR C8051F336
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F336DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: USB, UART
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F336
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1430

C8051F336/7/8/9
21. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 21.1.
138
S
V
L
6
M
A
S
T
E
R
S
V
Interrupt
Request
L
5
M
O
T
X
D
E
SMB0ADR
S
L
V
4
SMB0CN
S
T
A
S
V
L
3
S
O
T
S
V
L
2
Q
A
C
K
R
S
L
V
1
R
O
A
B
L
S
T
S
V
L
0
A
C
K
G
C
S
I
S
V
M
L
6
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
Hardware ACK Generation
IRQ Generation
M
S
V
SMBUS CONTROL LOGIC
L
5
SMB0ADM
M
S
L
V
4
S
V
M
L
3
Figure 21.1. SMBus Block Diagram
M
S
V
L
2
M
E
N
S
B
M
S
L
V
1
N
H
I
S
V
M
L
0
SMB0CF
B
U
S
Y
E
H
A
C
K
O
E
X
T
H
D
L
M
O
S
B
T
E
M
S
B
E
F
T
M
S
B
C
S
1
7
M
C
S
B
S
0
6
Data Path
SMB0DAT
5
Control
4
3
Rev.1.0
2
1
0
00
01
10
11
Control
SDA
Control
SCL
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
FILTER
FILTER
2
N
N
C serial bus. Reads and writes to
SDA
SCL
C
R
O
R
S
S
B
A
Port I/O