C8051F336DK Silicon Laboratories Inc, C8051F336DK Datasheet - Page 119

• Manufacturer Part Number: C8051F336DK
• Description: DEV KIT FOR C8051F336
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F336DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: USB, UART
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F336
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1430

20. Port Input/Output
Digital and analog resources are available through 17 (C8051F336/7) or 21 (C8051F338/9) I/O pins. Port
pins P0.0-P2.3 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources, or assigned to an analog function as shown in Figure 20.4. Port pin P2.4 on the C8051F338/9
and P2.0 on the C8051F336/7 can be used as GPIO and are shared with the C2 Interface Data signal
(C2D). The designer has complete control over which functions are assigned, limited only by the number of
physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar
Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regard-
less of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.4 and Figure 20.5). The registers XBR0 and XBR1, defined in SFR Definition 20.1 and SFR
Definition 20.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
P2
PCA
CP0
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.3*)
Figure 20.1. Port I/O Functional Block Diagram
2
4
2
2
4
2
8
8
4
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
Section “6. Electrical Characteristics” on page
Rev.1.0
(ADC0, CP0, VREF, XTAL)
To Analog Peripherals
8
8
4
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Cells
Cells
Cell
I/O
I/O
I/O
P0
P1
P2
C8051F336/7/8/9
External Interrupts
PnMDIN Registers
EX0 and EX1
PnMDOUT,
*P2.0-P2.3 are only available through
the crossbar on QFN24 Packages.
P0.0
P0.7
P1.0
P1.7
P2.0*
P2.3*
27.
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