C8051F336DK Silicon Laboratories Inc, C8051F336DK Datasheet - Page 103

• Manufacturer Part Number: C8051F336DK
• Description: DEV KIT FOR C8051F336
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F336DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: USB, UART
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F336
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1430

SFR Definition 17.1. VDM0CN: V
SFR Address = 0xFF
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See
tics” on page 27
external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
Name
Reset
Bit
5:0
Type
7
6
Bit
VDDSTAT
UNUSED
VDMEN
VDMEN
Name
Varies
R/W
7
for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an
VDDSTAT
V
This bit turns the V
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 17.2). Selecting the V
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
reset source.
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
Unused. Read = 000000b; Write = Don’t care.
Varies
DD
DD
R
6
DD
DD
DD
DD
Monitor Enable.
Status.
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
R
5
0
DD
DD
DD
monitor circuit on/off. The V
Monitor Control
monitor threshold.
DD
Rev.1.0
R
4
0
DD
monitor threshold.
monitor as a reset source before it has stabilized
Function
R
3
0
Section “6. Electrical Characteris-
C8051F336/7/8/9
DD
R
2
0
DD
DD
Monitor cannot generate sys-
Monitor and selecting it as a
Monitor output).
R
1
0
R
0
0
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